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AM3874 Datasheet(PDF) 276 Page - Texas Instruments |
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AM3874 Datasheet(HTML) 276 Page - Texas Instruments |
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276 / 361 page  AM3874, AM3871 SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013 www.ti.com Table 8-51. DDR2/DDR3 PHY Registers (continued) DDR0 HEX DDR1 HEX ACRONYM REGISTER NAME ADDRESS ADDRESS 0x47C0_C460 0x47C0_C860 CMD1_REG_PHY_INVERT_CLKOUT_0 DDR PHY Command 1 Invert Clockout Selection Register 0x47C0_C484 0x47C0_C884 CMD2_REG_PHY_CTRL_SLAVE_RATIO_0 DDR PHY Command 2 Address/Command Slave Ratio Register 0x47C0_C490 0x47C0_C890 CMD2_REG_PHY_DLL_LOCK_DIFF_0 DDR PHY Command 2 Address/Command DLL Lock Difference Register 0x47C0_C494 0x47C0_C894 CMD2_REG_PHY_INVERT_CLKOUT_0 DDR PHY Command 2 Invert Clockout Selection Register 0x47C0_C4C8 0x47C0_C8C8 DATA0_REG_PHY_RD_DQS_SLAVE_RATIO _0 DDR PHY Data Macro 0 Read DQS Slave Ratio Register 0x47C0_C4DC 0x47C0_C8DC DATA0_REG_PHY_WR_DQS_SLAVE_RATI O_0 DDR PHY Data Macro 0 Write DQS Slave Ratio Register 0x47C0_C4F0 0x47C0_C8F0 DATA0_REG_PHY_WRLVL_INIT_RATIO_0 DDR PHY Data Macro 0 Write Leveling Init Ratio Register 0x47C0_C4F8 0x47C0_C8F8 DATA0_REG_PHY_WRLVL_INIT_MODE_0 DDR PHY Data Macro 0 Write Leveling Init Mode Ratio Selection Register 0x47C0_C4FC 0x47C0_C8FC DATA0_REG_PHY_GATELVL_INIT_RATIO_0 DDR PHY Data Macro 0 DQS Gate Training Init Ratio Register 0x47C0_C504 0x47C0_C904 DATA0_REG_PHY_GATELVL_INIT_MODE_0 DDR PHY Data Macro 0 DQS Gate Training Init Mode Ratio Selection Register 0x47C0_C508 0x47C0_C908 DATA0_REG_PHY_FIFO_WE_SLAVE_RATI O_0 DDR PHY Data Macro 0 DQS Gate Slave Ratio Register 0x47C0_C51C 0x47C0_C91C DATA0_REG_PHY_DQ_OFFSET_0 Offset Value From DQS to DQ for Data Macro 0 0x47C0_C520 0x47C0_C920 DATA0_REG_PHY_WR_DATA_SLAVE_RATI O_0 DDR PHY Data Macro 0 Write Data Slave Ratio Register 0x47C0_C534 0x47C0_C934 DATA0_REG_PHY_USE_RANK0_DELAYS DDR PHY Data Macro 0 Delay Selection Register 0x47C0_C538 0x47C0_C938 DATA0_REG_PHY_DLL_LOCK_DIFF_0 DDR PHY Data Macro 0 DLL Lock Difference Register 0x47C0_C56C 0x47C0_C96C DATA1_REG_PHY_RD_DQS_SLAVE_RATIO _0 DDR PHY Data Macro 1 Read DQS Slave Ratio Register 0x47C0_C580 0x47C0_C980 DATA1_REG_PHY_WR_DQS_SLAVE_RATI O_0 DDR PHY Data Macro 1 Write DQS Slave Ratio Register 0x47C0_C594 0x47C0_C994 DATA1_REG_PHY_WRLVL_INIT_RATIO_0 DDR PHY Data Macro 1 Write Leveling Init Ratio Register 0x47C0_C59C 0x47C0_C99C DATA1_REG_PHY_WRLVL_INIT_MODE_0 DDR PHY Data Macro 1 Write Leveling Init Mode Ratio Selection Register 0x47C0_C5A0 0x47C0_C9A0 DATA1_REG_PHY_GATELVL_INIT_RATIO_0 DDR PHY Data Macro 1 DQS Gate Training Init Ratio Register 0x47C0_C5A8 0x47C0_C9A8 DATA1_REG_PHY_GATELVL_INIT_MODE_0 DDR PHY Data Macro 1 DQS Gate Training Init Mode Ratio Selection Register 0x47C0_C5AC 0x47C0_C9AC DATA1_REG_PHY_FIFO_WE_SLAVE_RATI O_0 DDR PHY Data Macro 1 DQS Gate Slave Ratio Register 0x47C0_C5C0 0x47C0_C9C0 DATA1_REG_PHY_DQ_OFFSET_1 Offset Value From DQS to DQ for Data Macro 1 0x47C0_C5C4 0x47C0_C9C4 DATA1_REG_PHY_WR_DATA_SLAVE_RATI O_0 DDR PHY Data Macro 1 Write Data Slave Ratio Register 0x47C0_C5D8 0x47C0_C9D8 DATA1_REG_PHY_USE_RANK0_DELAYS DDR PHY Data Macro 1 Delay Selection Register 0x47C0_C5DC 0x47C0_C9DC DATA1_REG_PHY_DLL_LOCK_DIFF_0 DDR PHY Data Macro 1 DLL Lock Difference Register 276 Peripheral Information and Timings Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM3874 AM3871 |
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