AM3874 datasheet(278/361 Pages) TI

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DDR[x]_CLK

AM3874, AM3871

SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013

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Table 8-52. DDR-Related Control Module Registers (continued)

HEX ADDRESS RANGE

ACRONYM

0x4814 0E0C

DDR_VTP_CTRL_0

DDR0 VTP Control Register

0x4814 0E10

DDR_VTP_CTRL_1

DDR1 VTP Control Register

8.13.4 DDR2/DDR3 Memory Controller Electrical Data/Timing

TI only supports board designs that follow the DDR2 and DDR3 Routing Specifications outlined in this

document. The switching characteristics and the timing diagram for the DDR2 memory controller are

shown in Table 8-53 and Figure 8-46.

Table 8-53. Switching Characteristics Over Recommended Operating Conditions for DDR2/DDR3 Memory

Controller (1)

OPP100/120/166

NO.

UNIT

MIN

MAX

DDR2 mode

2.5

tc(DDR_CLK)

Cycle time, DDR[x]_CLK

DDR3 mode

1.876

(1)

The PLL_DDR Controller must be programmed such that the resulting DDR[x]_CLK clock frequency is within the specified range.

Figure 8-46. DDR2/DDR3 Memory Controller Clock Timing

8.13.4.1 DDR2 Routing Specifications

8.13.4.1.1 DDR2 Interface

This section provides the timing specification for the DDR2 interface as a PCB design and manufacturing

specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,

and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need

for a complex timing closure process. For more information regarding the guidelines for using this DDR2

specification, see the Understanding TI’s PCB Routing Rule-Based DDR Timing Specification Application

Report (Literature Number: SPRAAV0).

8.13.4.1.1.1 DDR2 Interface Schematic

Figure 8-47 shows the DDR2 interface schematic for a x32 DDR2 memory system. In Figure 8-48 the x16

DDR2 system schematic is identical except that the high-word DDR2 device is deleted.

When not using all or part of a DDR2 interface, the proper method of handling the unused pins is to tie off

the DDR[x]_DQS[n] pins to the corresponding DVDD_DDR[x] supply via a 1k-

Ω resistor and pulling the

DDR[x]_DQS[n] pins to ground via a 1k-

Ω resistor. This needs to be done for each byte not used. Also,

include the 50-

Ω pulldown for DDR[x]_VTP. The DVDD_DDR[x] and VREFSSTL_DDR[x] power supply

pins need to be connected to their respective power supplies even if DDR[x] is not being used. All other

DDR interface pins can be left unconnected. Note that the supported modes for use of the DDR EMIF are

32-bits wide, 16-bits wide, or not used.

278

Peripheral Information and Timings

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