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AM3874 Datasheet(PDF) 277 Page - Texas Instruments |
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AM3874 Datasheet(HTML) 277 Page - Texas Instruments |
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277 / 361 page  AM3874, AM3871 www.ti.com SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013 Table 8-51. DDR2/DDR3 PHY Registers (continued) DDR0 HEX DDR1 HEX ACRONYM REGISTER NAME ADDRESS ADDRESS 0x47C0_C610 0x47C0_CA10 DATA2_REG_PHY_RD_DQS_SLAVE_RATIO _0 DDR PHY Data Macro 2 Read DQS Slave Ratio Register 0x47C0_C624 0x47C0_CA24 DATA2_REG_PHY_WR_DQS_SLAVE_RATI O_0 DDR PHY Data Macro 2 Write DQS Slave Ratio Register 0x47C0_C638 0x47C0_CA38 DATA2_REG_PHY_WRLVL_INIT_RATIO_0 DDR PHY Data Macro 2 Write Leveling Init Ratio Register 0x47C0_C640 0x47C0_CA40 DATA2_REG_PHY_WRLVL_INIT_MODE_0 DDR PHY Data Macro 2 Write Leveling Init Mode Ratio Selection Register 0x47C0_C644 0x47C0_CA44 DATA2_REG_PHY_GATELVL_INIT_RATIO_0 DDR PHY Data Macro 2 DQS Gate Training Init Ratio Register 0x47C0_C64C 0x47C0_CA4C DATA2_REG_PHY_GATELVL_INIT_MODE_0 DDR PHY Data Macro 2 DQS Gate Training Init Mode Ratio Selection Register 0x47C0_C650 0x47C0_CA50 DATA2_REG_PHY_FIFO_WE_SLAVE_RATI O_0 DDR PHY Data Macro 2 DQS Gate Slave Ratio Register 0x47C0_C664 0x47C0_CA64 DATA2_REG_PHY_DQ_OFFSET_2 Offset value from DQS to DQ for Data Macro 2 0x47C0_C668 0x47C0_CA68 DATA2_REG_PHY_WR_DATA_SLAVE_RATI O_0 DDR PHY Data Macro 2 Write Data Slave Ratio Register 0x47C0_C67C 0x47C0_CA7C DATA2_REG_PHY_USE_RANK0_DELAYS DDR PHY Data Macro 2 Delay Selection Register 0x47C0_C680 0x47C0_CA80 DATA2_REG_PHY_DLL_LOCK_DIFF_0 DDR PHY Data Macro 2 DLL Lock Difference Register 0x47C0_C6B4 0x47C0_CAB4 DATA3_REG_PHY_RD_DQS_SLAVE_RATIO _0 DDR PHY Data Macro 3 Read DQS Slave Ratio Register 0x47C0_C6C8 0x47C0_CAC8 DATA3_REG_PHY_WR_DQS_SLAVE_RATI O_0 DDR PHY Data Macro 3 Write DQS Slave Ratio Register 0x47C0_C6DC 0x47C0_CADC DATA3_REG_PHY_WRLVL_INIT_RATIO_0 DDR PHY Data Macro 3 Write Leveling Init Ratio Register 0x47C0_C6E4 0x47C0_CAE4 DATA3_REG_PHY_WRLVL_INIT_MODE_0 DDR PHY Data Macro 3 Write Leveling Init Mode Ratio Selection Register 0x47C0_C6E8 0x47C0_CAE8 DATA3_REG_PHY_GATELVL_INIT_RATIO_0 DDR PHY Data Macro 3 DQS Gate Training Init Ratio Register 0x47C0_C6F0 0x47C0_CAF0 DATA3_REG_PHY_GATELVL_INIT_MODE_0 DDR PHY Data Macro 3 DQS Gate Training Init Mode Ratio Selection Register 0x47C0_C6F4 0x47C0_CAF4 DATA3_REG_PHY_FIFO_WE_SLAVE_RATI O_0 DDR PHY Data Macro 3 DQS Gate Slave Ratio Register 0x47C0_C708 0x47C0_CB08 DATA3_REG_PHY_DQ_OFFSET_3 Offset Value From DQS to DQ for Data Macro 3 0x47C0_C70C 0x47C0_CB0C DATA3_REG_PHY_WR_DATA_SLAVE_RATI O_0 DDR PHY Data Macro 3 Write Data Slave Ratio Register 0x47C0_C720 0x47C0_CB20 DATA3_REG_PHY_USE_RANK0_DELAYS DDR PHY Data Macro 3 Delay Selection Register 0x47C0_C724 0x47C0_CB24 DATA3_REG_PHY_DLL_LOCK_DIFF_0 DDR PHY Data Macro 3 DLL Lock Difference Register 8.13.3 DDR-Related Control Module Registers Description Table 8-52. DDR-Related Control Module Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x4814 0694 EMIF_CLK_GATE EMIF0/1 PHY Clock Gate Control Register 0x4814 0E04 DDR0_IO_CTRL DDR Memory Controller_0 IO Control Register 0x4814 0E08 DDR1_IO_CTRL DDR Memory Controller_1 IO Control Register Copyright © 2011–2013, Texas Instruments Incorporated Peripheral Information and Timings 277 Submit Documentation Feedback Product Folder Links: AM3874 AM3871 |
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