PXA270 datasheet(108/126 Pages) INTEL

108 / 126 page

6-44

Electrical, Mechanical, and Thermal Specification

Intel® PXA270 Processor

AC Timing Specifications

6.6

SSP Timing Specifications

Figure 6-29 describes the SSP timing parameters. The SSP pin timing specifications are referenced

to SSPCLK. Table 6-23 gives the values for the parameters.

Note: In Figure 6-29, read the term “tSFMV” as “TSTXV.”

Figure 6-30. Timing Diagram for SSP Slave Mode Transmitting Data to an External Peripheral

Figure 6-29. SSP Master Mode Timing Definitions

Table 6-23. SSP Master Mode Timing Specifications

Symbol

Description

Min

Max

Units

Notes

Tsfmv

SSPSCLK rise to SSPSFRM driven valid

Trxds

SSPRXD valid to SSPSCLK fall (input setup)

Trxdh

SSPSCLK fall to SSPRXD invalid (input hold)

Tsfmv

SSPSCLK rise to SSPTXD valid

SSPSCLK

SSPSFRM

SSPTXD

SSPRXD

Tsfmv

Trxds

Trxdh

PXA27x processor transmitting data

SSPSCLK

(from Peripheral)

SSPTXD

(from SSP)

PXA27x SSP (Slave Mode) transmitting data to external peripheral

SSPSFRM

(from Peripheral)

tSCLK2TXD_output_delay

tSFRM2TXD_output_delay

PXA27x processor transmitting data

SSPSCLK

(from Peripheral)

SSPTXD

(from SSP)

PXA27x SSP (Slave Mode) transmitting data to external peripheral

SSPSFRM

(from Peripheral)

tSCLK2TXD_output_delay

tSFRM2TXD_output_delay

PXA270 Datasheet(PDF) 108 Page - Intel Corporation

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