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PXA270 Datasheet(PDF) 110 Page - Intel Corporation |
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PXA270 Datasheet(HTML) 110 Page - Intel Corporation |
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110 / 126 page  6-46 Electrical, Mechanical, and Thermal Specification Intel® PXA270 Processor AC Timing Specifications §§ TBSIS1 Input Setup to TCK TDI, TMS 4.0 — ns — TBSIH1 Input Hold from TCK TDI, TMS 6.0 — ns — TBSIS2 Input Setup to TCK nTRST 25.0 — ns — TBSIH2 Input Hold from TCK nTRST 3.0 — ns — TnTRST Assertion time of nTRST 6 — ms — TBSOV1 TDO Valid Delay 1.5 6.9 ns Relative to falling edge of TCK TOF1 TDO Float Delay 1.1 5.4 ns Relative to falling edge of TCK Figure 6-32. JTAG Boundary-Scan Timing Table 6-26. Boundary Scan Timing Specifications (Sheet 2 of 2) Symbol Parameter Min Max Units Notes Shift-IR Run-Test/Idle TOF1 TBSOV1 TBSOV1 TBSOV1 TBSOV1 TBSOV1 TBSOV1 TBSOV1 TBSIH1 TBSIS1 TBSIH1 TBSIS1 TBSIH2 TBSIS2 TBSCL TBSCH TBSF TCK nTRST TMS TDI TDO Controller State TnTRST |
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