Special Features of the CPU
September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
107
11.0 Special Features of the CPU
11.1 Multiplier/Accumulator
A fast, on-chip signed 2’s complement MAC (Multiply/
Accumulate) function is provided to assist the main CPU
with digital signal processing applications. Multiply
results, as well as the lower 2 bytes of the Accumulator,
are available immediately after the input registers are
written. The upper 2 bytes require a single instruction
delay before reading. The MAC function is tied directly
on the internal data bus, and is mapped into the register
space. The following MAC block diagram provides data
flow information. The user has the choice to either cause
a multiply/accumulate function to take place, or a multi-
ply only function. The user selects which operation is
performed by the choice of input register. The multiply
function occurs immediately whenever the MUL_X or the
MUL_Y multiplier input registers are written, and the
result is available in the MUL_DH and MUL_DL multiplier
result registers. The Multiply/Accumulate function is exe-
cuted whenever there is a write to the MAC_X or the
MAC_Y Multiply/Accumulate input registers, and the
result is available in the ACC_DR3, ACC_DR2,
ACC_DR1, and ACC_DR0 accumulator result registers.
A write to MUL_X or MAC_X is input as the X value to
both the multiply and Multiply/Accumulate functions. A
write to MUL_Y or MAC_Y is input as the Y value to both
the multiply and Multiply/Accumulate functions. A write to
the MAC_CL0 or MAC_CL1 registers will clear the value
in the four accumulate registers.
Operation of the Multiply/Accumulate function relies on
proper multiplicand input. The first value of each multipli-
cand must be placed into MUL_X (or MUL_Y) register to
avoid causing a Multiply/Accumulate to occur. The sec-
ond multiplicand must be placed into MAC_Y (or
MAC_X) thereby triggering the Multiply/Accumulate
function.
MUL_X, MUL_Y, MAC_X, and MAC_Y are 8-bit signed
input registers. MUL_DL and MUL_DH form a 16-bit
signed output. ACC_DR0, ACC_DR1, ACC_DR2 and
ACC_DR3 form a 32-bit signed output.
An extra instruction must be inserted between the follow-
ing sequences of MAC operations to provide extra delay.
If this is not done, the Accumulator results will be inaccu-
rate.
a.
Two MAC instructions in succession:
mov reg[MAC_X],a
nop //add nop or any other instruction
mov reg[MAC_X],a
For sequence a., there is no workaround, the nop or
other instruction must be inserted.
b.
A MAC instruction followed by a read of the
most significant Accumulator bytes:
mov reg[MAC_X],a
nop //add nop or any other instruction
mov a,[ACC_DR2] // or ACC_DR3
For sequence b., the least significant Accumulator bytes
(ACC_DR0, ACC_DR1) may be reliably read directly
after the MAC instruction.
Writing to the multiplier registers (MUL_X, MUL_Y), and
reading the result back from the multiplier product regis-
ters (MUL_DH, MUL_DL), is not affected by this problem
and does not have any restrictions.
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