Special Features of the CPU
September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
111
This filter is implemented using a combination of hard-
ware and software resources. Hardware is used to accu-
mulate the high-speed in-coming data while the software
is used to process the lower speed, enhanced resolution
data for output.
Decimator Incremental Register (DEC_CR, Address = Bank 0, E6h)
Decimator High Register (DEC_DH / DEC_CL, Address = Bank 0, E4h)
Decimator Data Low Register (DEC_DL, Address = Bank 0, E5h)
Table 90:
Decimator/Incremental Control Register
Bit #
7
6
5
4
3
2
1
0
POR
0
0
0
0
0
0
0
0
Read/Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
IGEN [3]
IGEN [2]
IGEN [1]
IGEN [0]
ICCKSEL
DCol [1]
DCol [0]
DCLKSEL
Bit [7:4]
: IGEN [3:0] Individual enables for each analog column that gates the Analog Comparator based on the
ICCKSEL input (Bit 3)
Bit 3
: ICCKSEL Clock select for Incremental gate function
0 = Digital Basic Type A Block 02
1 = Digital Communications Type A Block 06
Bit [2:1]
: DCol [1:0] Selects Analog Column Comparator source
0 0 = Analog Column Comparator 0
0 1 = Analog Column Comparator 1
1 0 = Analog Column Comparator 2
1 1 = Analog Column Comparator 3
Bit 0
: DCLKSEL Clock select for Decimator latch
0 = Digital Basic Type A Block 02
1 = Digital Communications Type A Block 06
Table 91:
Decimator Data High Register
Bit #
7
6
5
4
3
2
1
0
POR
0
0
0
0
0
0
0
0
Read/Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
Data [7]
Data [6]
Data [5]
Data [4]
Data [3]
Data [2]
Data [1]
Data [0]
Bit [7:0]
: Data [7:0]
8-bit data value when read is the high order byte within the 16-bit decimator data registers
Any 8-bit data value when written will cause both the Decimator Data High (DEC_DH) and Decimator Data Low
(DEC_DL) registers to be cleared
Table 92:
Decimator Data Low Register
Bit #
7
6
5
4
3
2
1
0
POR
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Bit Name
Data [7]
Data [6]
Data [5]
Data [4]
Data [3]
Data [2]
Data [1]
Data [0]
Bit [7:0]
: Data [7:0]
8-bit data value when read is the low order byte within the 16 bit decimator data registers
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