Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
114
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
September 5, 2002
The Watchdog Timer period is automatically set to be 3
counts of the Sleep Timer overflows. This represents
between two and three sleep intervals depending on the
count in the Sleep Timer at the previous WDT clear.
When this timer reaches 3, a WDR is generated.
The user can either clear the WDT, or the WDT and the
Sleep Timer. Whenever the user writes to the Reset
WDT Register (RES_WDT), the WDT will be cleared. If
the data that is written is the hex value 38H, the Sleep
Timer will also be cleared at the same time.
This timer chain is also used to time the startup for the
external 32 kHz crystal oscillator. When selecting the
external 32 kHz oscillator, a value of 1 second must be
selected as the sleep interval. When the sleep interrupt
occurs, the 32 kHz oscillator source will switch from
internal to the crystal. The device does not have to be
put into sleep for this event to occur. Note that if too short
of a sleep interval is given, the crystal oscillator will not
be stable prior to switch over and the results will be
unpredictable.
Reset WDT Register (RES_WDT, Address = Bank 0, E3h)
11.4 Sleep States
There are three sleep states that can be used to lower
the overall power consumption on the device. The three
states are CPU Sleep, Analog Sleep, and Full Sleep.
The CPU can only be put to sleep by the firmware. This
is accomplished by setting the Sleep Bit in the Status
and Control Register (CPU_SCR). This stops the CPU
from executing instructions, and the CPU will remain
asleep until an interrupt comes pending, or there is a
reset event (either a Power On Reset, or a Watchdog
Timer Reset). While in the CPU Sleep state, all clocking
signals derived from the Internal Main Oscillator are
inactivated, including the 48M, 24M, 24V1, and 24V2
system clocking signals. The Internal Low Speed Oscilla-
tor will continue to operate during the CPU Sleep state.
The function of any analog or digital PSoC block that is
clocked from these system-clocking signals will stop dur-
ing the CPU Sleep state.
The user can also put all the analog PSoC block circuits
to sleep. This is accomplished by resetting the Analog
Array Power Control bits in the Analog Reference Con-
trol Register (ARF_CR), which overrides the individual
enable bits within each analog PSoC block. Setting the
Analog Array Power Control bits will restore the function
to those analog PSoC blocks that were previously in use.
The user should take into account the required settling
time after an analog PSoC block is enabled before it will
provide the maximum precision.
For greatest power savings, the user should put the
device in the Full Sleep state. This is accomplished by
first transitioning to the Analog Sleep state, and then set-
ting the Sleep Bit in the CPU_SCR Register to the Full
Sleep state. The CPU will be stopped at this point, and
either an interrupt or reset event is required to transition
back to the Analog Sleep state.
The Voltage Reference and Supply Voltage Monitor drop
into (fully functional) power-reduced states. All interrupts
remain active. The Internal Low Speed Oscillator
remains running (it will however drop into a less accu-
rate, low-power state). If enabled, the External Crystal
Oscillator will continue running throughout sleep (the
Internal Low Speed Oscillator is disabled if the External
Crystal Oscillator is selected). Only the occurrence of an
Table 94:
Reset WDT Register
Bit #
7
6
5
4
3
2
1
0
POR
0
0
0
0
0
0
0
0
Read/Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
Data [7]
Data [6]
Data [5]
Data [4]
Data [3]
Data [2]
Data [1]
Data [0]
Bit [7:0]
: Data [7:0] Any write to this register will clear Watchdog Timer, a write of 38h will also clear the Sleep Timer
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
