Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
116
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
September 5, 2002
11.5 Supply Voltage Monitor
The Supply Voltage Monitor detector generates an inter-
rupt whenever Vcc drops below a pre-programmed
value. There are eight voltage trip points that are select-
able by setting the VM [2:0] bit in the Voltage Monitor
Control Register (VLT_CR). These bits also select the
Switch Mode Pump trip points. The Supply Voltage Mon-
itor will remain active when the device enters sleep
mode.
Voltage Monitor Control Register (VLT_CR, Address = Bank 1, E3h)
Table 95:
Voltage Monitor Control Register
Bit #
7
6
5
4
3
2
1
0
POR
0
0
0
0
0
0
0
0
Read/
Write
W
RW
--
--
--
W
W
W
Bit Name
SMP
Reserved
Reserved
Reserved
Reserved
VM [2]
VM [1]
VM [0]
Bit 7
: SMP Disables SMP function
0 = Switch Mode Pump enabled, default
1 = Switch Mode Pump disabled
Bit 6
: Reserved
Bit 5
: Reserved
Bit 4
: Reserved
Bit 3
: Reserved
Bit [2:0]
: VM [2:0]
Low Voltage Detection
Switch Mode Pump
0 0 0 = 2.95 Trip Voltage1 0 0 0 = 3.17 Trip Voltage
0 0 1 = 3.02 Trip Voltage 0 0 1 = 3.25 Trip Voltage
0 1 0 = 3.17 Trip Voltage 0 1 0 = 3.42 Trip Voltage
0 1 1 = 3.71 Trip Voltage 0 1 1 = 3.94 Trip Voltage
1 0 0 = 4.00 Trip Voltage 1 0 0 = 4.19 Trip Voltage
1 0 1 = 4.48 Trip Voltage 1 0 1 = 4.64 Trip Voltage
1 1 0 = 4.56 Trip Voltage 1 1 0 = 4.82 Trip Voltage
1 1 1 = 4.64 Trip Voltage 1 1 1 = 5.00 Trip Voltage
1.
Voltages are ideal typical values. Tolerances are in Table 103 on page 127.
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