Special Features of the CPU
September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
117
11.6 Switch Mode Pump
This feature is available on the CY8C26xxx versions
within this family. During the time Vcc is ramping from 0
Volts to POR Vtrip (2.2V +/- 12%), IC operation is held off
by the POR circuit and the Switch Mode Pump is
enabled. The pump is realized by connecting an external
inductor between the battery voltage and SMP, with an
external diode pointing from SMP to the Vcc pin (which
must have a bypass capacitance of at least 0.1uF con-
nected to Vcc). This circuitry will pump Vcc to the Switch
Mode Pump value specified in the Voltage Monitor Con-
trol Register (VLT_CR), shown above. Battery voltage
values down to 0.9 V during operation are supported, but
this circuitry is not guaranteed to start for battery volt-
ages below 1.2 V. Once the IC is enabled after its power
up and boot sequence, firmware can disable the SMP
function by writing Voltage Monitor Control Register
(VLT_CR) bit 7 to a 1.
When the IC is put into sleep mode, the power supply
pump will remain running to maintain voltage. This may
result in higher than specification sleep current depend-
ing upon application. If the user desires, the pump may
be disabled during precision measurements (such as A/
D conversions) and then re-enabled (writing B7 to 1 and
then back to 0 again). The user, however, is responsible
for making the operation happen quickly enough to guar-
antee supply holdup (by the bypass capacitor) sufficient
for continued operation.
Figure 32: Switch Mode Pump
To Rest Of
Circuitry
X
RST
SMP
SMP
Control
Logic
SMP Reset
Reset
Power For All Circuitry
V
CC
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