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Special Features of the CPU
September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
119
Notes
:
NA: Not applicable
*: Indeterminate
Blk ID: Number of 64-byte block within FLASH memory space
Clock: CPU system clocking signal value
Pointer: Address of first byte of 64-byte block within SRAM memory space
TV: Table value
Table 97:
CY8C25122, CY8C26233, CY8C26443, CY8C26643 (256 Bytes of SRAM)
Operation
Function
Input SRAM Data
Output SRAM Data
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
Reset1
1.
This is a software-only reset.
Calibrates
then sets
PC and SP
values to 0
00
NA
NA
NA
NA
NA
NA
NA
NA
*
*
*
*
*
*
*
*
Read Block
Move block
of 64 bytes
of FLASH
data into
SRAM
01
3Ah
SP
+3
Blk
ID
Pointer
NA
0
0
0
0
0
*
*
*
*
*
*
Write Block2
2.
This operation should only be invoked by calling a function in the FlashBlock library. Device specifications are no
longer guaranteed if this function is directly called by the user’s code
.
Program
block of
FLASH with
data from
SRAM
02
3Ah
SP
+3
Blk
ID
Pointer
Clock
0
0
0
0
0
*
*
*
*
*
*
Erase Block
Erase block
of FLASH
03
3Ah
SP
+3
Blk
ID
NA
Clock
0
0
0
0
0
*
*
*
*
*
*
Protect Block3
3.
This function can only be invoked by the device programmer, not by user’s code.
Set memory
protection
bits4
4.
The address is hard coded by algorithm.
04
3Ah
SP
+3
NA
NA
Clock
0
0
0
0
0
*
*
*
*
*
*
Erase All3
Erase all
FLASH data
05
3Ah
SP
+3
NA
NA
Clock
0
0
0
0
0
*
*
*
*
*
*
Table Read
Read device
type code
06
3Ah
SP
+3
Tbl
ID
NA
NA
NA
NA
NA
TV
(0)
TV
(1)
TV
(2)
TV
(3)
TV
(4)
TV
(5)
TV
(6)
TV
(7)
Checksum
Calculate
FLASH
checksum
for data
range speci-
fied
07
3Ah
SP
+3
Blk
Cou
nter
NA
NA
0
0
0
CS
H
CSL
*
*
*
*
*
*
Calibrate5
5.
User-writeable registers include Main Oscillator Trim (IMO_TR), Internal Low Speed Oscillator Trim (ILO_TR), and
Bandgap Trim (BDG_TR).
Sets user-
writable reg-
isters to
default
08
3Ah
SP
+3
NA
NA
NA
0
0
*
*
*
*
*
*