WM5102 datasheet(126/334 Pages) WOLFSON

126 / 334 page

WM5102

Production Data

PD, June 2014, Rev 4.2

126

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

AIF3TX_LRCLK_I

AIF3 Audio Interface TX path LRCLK

Invert

0 = AIF3TXLRCLK not inverted

1 = AIF3TXLRCLK inverted

AIF3TX_LRCLK_

FRC

AIF3 Audio Interface TX path LRCLK

Output Control

0 = Normal

1 = AIF3TXLRCLK always enabled in

Master mode

AIF3TX_LRCLK_

MSTR

AIF3 Audio Interface TX path LRCLK

Master Select

0 = AIF3TXLRCLK Slave mode

1 = AIF3TXLRCLK Master mode

R1410

(0582h)

AIF3 Rx

Pin Ctrl

AIF3RX_LRCLK_

INV

AIF3 Audio Interface LRCLK Invert

0 = AIF3RXLRCLK not inverted

1 = AIF3RXLRCLK inverted

AIF3RX_LRCLK_

FRC

AIF3 Audio Interface LRCLK Output

Control

0 = Normal

1 = AIF3RXLRCLK always enabled in

Master mode

AIF3RX_LRCLK_

MSTR

AIF3 Audio Interface LRCLK Master

Select

0 = AIF3RXLRCLK Slave mode

1 = AIF3RXLRCLK Master mode

Table 31 AIF3 Master / Slave Control

AIF SIGNAL PATH ENABLE

The AIF1 interface supports up to 8 input (RX) channels and up to 8 output (TX) channels. Each of

these channels can be enabled or disabled using the register bits defined in Table 32.

The AIF2 and AIF3 interfaces support up to 2 input (RX) channels and up to 2 output (TX) channels.

Each of these channels can be enabled or disabled using the register bits defined in Table 33 and

Table 34.

The system clock, SYSCLK, must be configured and enabled before any audio path is enabled. The

ASYNCCLK may also be required, depending on the path configuration. See “Clocking and Sample

Rates” for details of the system clocks.

The WM5102 performs automatic checks to confirm that the SYSCLK and ASYNCCLK frequencies

are high enough to support the commanded signal paths and processing functions. If an attempt is

made to enable an AIF signal path, and there are insufficient SYSCLK or ASYNCCLK cycles to

support it, then the attempt will be unsuccessful. (Note that any signal paths that are already active

will not be affected under these circumstances.)

The Underclocked Error conditions can be monitored using the GPIO and/or Interrupt functions. See

“General Purpose Input / Output” and “Interrupts” for further details.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1305

(0519h)

AIF1 Tx

Enables

AIF1TX8_ENA

AIF1 Audio Interface TX Channel 8 Enable

0 = Disabled

1 = Enabled

AIF1TX7_ENA

AIF1 Audio Interface TX Channel 7 Enable

0 = Disabled

1 = Enabled

WM5102 Datasheet(PDF) 126 Page - Wolfson Microelectronics plc

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