WM5102 datasheet(129/334 Pages) WOLFSON

129 / 334 page

Production Data

WM5102

PD, June 2014, Rev 4.2

129

AIF BCLK AND LRCLK CONTROL

The AIFnBCLK frequency is selected by the AIFn_BCLK_FREQ register. For each value of this

rate or a 44.1kHz-related sample rate, as described below.

If AIFn_RATE<1000 (see Table 21), then AIFn is referenced to the SYSCLK clocking domain and the

applicable frequency depends upon the SAMPLE_RATE_1, SAMPLE_RATE_2 or SAMPLE_RATE_3

registers.

If AIFn_RATE≥1000, then AIFn is referenced to the ASYNCCLK clocking domain and the applicable

frequency depends upon the ASYNC_SAMPLE_RATE_1 or ASYNC_SAMPLE_RATE_2 registers.

The selected AIFnBCLK rate must be less than or equal to SYSCLK/2, or ASYNCCLK/2, as

applicable. See “Clocking and Sample Rates” for details of SYSCLK and ASYNCCLK domains, and

the associated control registers.

The AIFnRXLRCLK frequency is controlled relative to AIFnBCLK by the AIFnRX_BCPF divider.

Under default conditions, the AIFn input (RX) and output (TX) paths both use the AIFnRXLRCLK

signal as the frame synchronisation clock. The AIFn output (TX) interface can be configured to use a

separate frame clock, AIFnTXLRCLK, using the AIFnTX_LRCLK_SRC bit, as described in Table 29,

Table 30 and Table 31 for AIF1, AIF2 and AIF3 respectively.

When the GPIOn pin is configured as AIFnTXLRCLK, then the AIFnTXLRCLK frequency is controlled

relative to AIFnBCLK by the AIFnTX_BCPF divider. See “General Purpose Input / Output” for details

of how to configure the GPIO1, GPIO2 or GPIO3 pins.

Note that the BCLK rate must be configured in Master or Slave modes, using the AIFn_BCLK_FREQ

registers. The LRCLK rate(s) only require to be configured in Master mode.

WM5102 Datasheet(PDF) 129 Page - Wolfson Microelectronics plc