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WM5102 Datasheet(PDF) 332 Page - Wolfson Microelectronics plc |
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WM5102 Datasheet(HTML) 332 Page - Wolfson Microelectronics plc |
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332 / 334 page  WM5102 Production Data w PD, June 2014, Rev 4.2 332 REVISION HISTORY DATE REV DESCRIPTION OF CHANGES PAGE CHANGED BY 05/04/12 1.0 Initial version PH 18/04/12 2.0 HPDET_STS, MICDET_STS deleted PWM_CLK_SEL description updated (50MHz option deleted). PH 08/06/12 2.0 Sample rates greater than 192kHz deleted. Power Domain information added. DCVDD & Configuration requirements for 50MHz clocking added. Electrical Characteristics updated (min/max limits deleted). FLL Synchroniser timing requirements added. DMICCLK, SPKCLK, BCLK timing requirements updated. LRA_FREQ register description updated (Haptics). Added details of the supported Sample Rates for different blocks. Additional details of SLIMbus clocking & Framer functions. Output Path noise gate function added. ECI_JD_SRC register deleted. ECI_BIAS_SRC register updated, noting permitted configurations of ECI digital/analogue bias sources. LDO2_ENA and LDO2_BYPASS register deleted – these are slaved to the CP2 controls. Clocking Configuration Applications Info updated to incorporate SLIMbus interface options. Analogue connections updated on External Components figure. PH 03/07/12 2.0 Update to GPIO FLL clock output: FLLn_GPCLK_DIV controls the frequency relative to Fvco, ie. independent of FLLn_OUTDIV. Volume Ramp register descriptions updated. Maximum LDO2 output voltage amended to 3.25V. PH 30/07/12 2.0 DRC2 deleted HP_CLK_DIV register deleted GP_DBTIME register updated DSP Firmware memory definitions updated MICBIAS description moved to Charge Pump & Regulator section. PH 05/10/12 2.0 Package Drawing updated. Input Pin descriptions corrected. SUBSYS_MAX_FREQ bit, and associated LDO requirements added, enabling 49.152MHz DSP clocking.. Noted Left-Justified and DSP-B modes valid in Master mode only. Maximum LDO2 output voltage reverted to 3.3V. Electrical Characteristics updated. Noted MICVDD required for analogue inputs. Changed descriptions of Input PGA & Output PGA ramp control registers. Typical AIF system connections updated. Noted AIF format is 2’s complement. Noted LRCLK rate registers only applicable in Slave mode. Noted MICVDD required for accessory detection. Deleted 64kHz & 128kHz audio sample rates. Noted 32kHz clock required for CP2. PH 15/10/12 2.0 Rev B silicon updates added: Support for second ASYNCCLK sample rate. Write Sequencer trigger function from DRC Signal Detect added. Enhancement to Headphone Impedance measurement. Added MICDET clamp and associated WKUP/WSEQ controls. Input pin maximum ratings updated; recommended to use Right channel analogue mic paths when using accessory detect. PH |
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