WM5102 datasheet(333/334 Pages) WOLFSON

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Production Data

WM5102

PD, June 2014, Rev 4.2

333

DATE

REV

DESCRIPTION OF CHANGES

PAGE

CHANGED BY

18/10/12

2.0

Package Drawing updated.

I2C timing diagram updated, with additional “SDA Valid” parameter.

13/11/12

2.0

Electrical Characteristics updated.

OUT[1-4]_OSR register bits deleted.

OUTnx_PGA_VOL registers deleted.

Correction to Pin Numbering (SPKOUTLP, SPKOUTLN, SPKOUTRP,

SPKOUTRN)

14/12/12

3.0

Updates describing automatic gain in AEC Loopback path.

Package drawing updated.

Generic description added for digital core mixer control registers.

Typical power consumption data added

19/02/13

3.0

Electrical Characteristics updated.

ESD diode configuration details added for external outputs.

OUT4_OSR register bit reinstated.

20/03/13

4.0

FLL Gain and Bandwidth control registers added.

DSP Firmware memory reset conditions amended (including

DSP1_MEM_ENA description).

DMA register control requirements added for disabling DSP.

08/05/13

4.0

Deleted statements about automatic thermal shutdown - speaker drivers

must be disabled via software control.

IM_BOOT_DONE_EINT2 updated (default is 0 - unmasked)

10/07/13

4.1

Power-up timing and Reset requirements updated.

SNR test conditions clarified.

Headphone impedance measurement control sequence updated;

HP_IMPEDANCE_RANGE updated;

HP_DACVAL added, HP_LVL deleted.

MEMS microphone connection description added.

DSP_IRQn bits added.

DAC output path now supports sample rates up to192kHz.

SLIMbus description added, including supported messages.

SLIMbus port configuration registers added.

OUTn_OSR and DACn_FREQ_LIM registers added for optimising

Headphone and Earpiece paths.

MICD_PD register deleted.

Clarifications to Sleep/Wake-Up control, including the LDOENA pin.

Noted that Control Sequence on Wake-Up is not supported.

User boot sequence is not supported.

FLLn_CTRL_UPD and associated descriptions updated.

Added details of register configuration sequence - required on POR,

HW Reset, SW Reset & Wake-Up.

06/12/13

4.1

Noted that MICVDD (output) can be used to power external mics.

Clarification to maximum input signal levels (analogue & digital).

Thermal characteristics added.

Noted DRC function supports sample rates up to 96kHz only.

DSP firmware requirements clarified; DMA and JTAG added.

Noted GPIO5 functions are different to GPIO1,2,3,4.

GPIO WSEQ output description updated

FLL free-running mode description updated

Noted LDO1 cannot be used to power external circuits.

Added clarifications and summary of memory/register status following

POR, HW Reset, SW Reset, and Sleep.

29/01/14

4.1

MCLK2 sleep mode frequency limit added.

SLIMbus Interface Timing details added.

48kHz BCLK support deleted

Clarification of Sleep mode clocking requirements.

SPK1_FMT definition amended.

WM5102 Datasheet(PDF) 333 Page - Wolfson Microelectronics plc

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