WM8998 datasheet(36/307 Pages) WOLFSON

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WM8998

Production Data

PD, October 2014, Rev 4.0

SLIMBUS INTERFACE TIMING

SLIMDAT

TDV

TCLKIL

TCKLIH

VIH

VIL

TSETUP

VIH

VIL

SLIMCLK

VIL, VIH are the 35%/65% levels of the respective inputs.

The SLIMDAT output delay (TDV) is with respect to the input pads of all receiving devices.

Figure 9 SLIMbus Interface Timing

The signal timing information shown in Figure 9 describe the timing requirements of the SLIMbus

interface as a whole, not just the WM8998 device. Accordingly, the following should be noted:

•

TDV is the propagation delay from the rising SLIMCLK edge (at WM8998 input) to the

SLIMDAT output being achieved at the input to all devices across the bus.

•

TSETUP is the set-up time for SLIMDAT input (at WM8998), relative to the falling SLIMCLK

edge (at WM8998).

•

TH is the hold time for SLIMDAT input (at WM8998) relative to the falling SLIMCLK edge (at

WM8998).

For more details of the interface timing, refer to the MIPI Alliance Specification for Serial Low-power

Inter-chip Media Bus (SLIMbus).

Test Conditions

The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

SLIMCLK Input

SLIMCLK cycle time

SLIMCLK pulse width high

TCLKIH

SLIMCLK pulse width low

TCLKIL

SLIMDAT Input

SLIMDAT setup time to SLIMCLK falling edge

TSETUP

3.5

SLIMDAT hold time from SLIMCLK falling edge

SLIMDAT Output

SLIMDAT time for data

output valid (wrt SLIMCLK

rising edge)

CLOAD = 15pF,

VDBVDD1 = 1.62V

TDV

6.7

8.6

CLOAD = 35pF,

VDBVDD1 = 1.62V

9.8

12.5

SLIMDAT slew rate

(20% to 80%)

CLOAD = 15pF

SRDATA

0.54 x

VDBVDD1

V/ns

CLOAD = 35pF

0.34 x

VDBVDD1

Other Parameters

Driver disable time

TDD

Bus holder output impedance

0.1 x VDBVDD1 < V <

0.9 x VDBVDD1

RDATAS

kΩ

WM8998 Datasheet(PDF) 36 Page - Wolfson Microelectronics plc

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