WM8998 datasheet(42/307 Pages) WOLFSON

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WM8998

Production Data

PD, October 2014, Rev 4.0

ANALOGUE LINE INPUT

Line inputs can be connected to the WM8998 in a similar manner to the microphone inputs described

above. Single-ended and differential modes are supported on each of the six analogue input paths.

The applicable mode (single-ended or differential) is selected using the INnx_SRC registers, as

described later.

The analogue line input configurations are illustrated in Figure 15 and Figure 16. Note that the

microphone bias (MICBIAS) is not used for line input connections.

GND

Line

To ADC

PGA

VMID

IN1AxN,

IN1BxN,

IN2AN,

IN2BN

IN1AxP,

IN1BxP,

IN2AP,

IN2BP

To ADC

PGA

VMID

IN1AxN,

IN1BxN,

IN2AN,

IN2BN

IN1AxP,

IN1BxP,

IN2AP,

IN2BP

Line

Figure 15 Single-Ended Line Input

Figure 16 Differential Line Input

DIGITAL MICROPHONE INPUT

Up to three digital microphones can be connected to the WM8998. The digital microphone mode is

selected using the INn_MODE registers, as described later. Note that the IN1_MODE setting is

applicable to a stereo pair of inputs; the Left and Right channels of any stereo pair of inputs are

always in the same mode.

In digital microphone mode, audio data is input on the DMICDAT1 or DMICDAT2 pins. The

DMICDAT1 pin carries two multiplexed channels of audio data; the DMICDAT2 pin supports a single

channel of audio data. These interfaces are clocked using the respective DMICCLK1 or DMICCLK2

pin.

When digital microphone input is enabled, the WM8998 outputs a clock signal on the applicable

DMICCLKn pin(s). The DMICCLKn frequency is controlled by the respective INn_OSR register, as

described in Table 1. See Table 3 for details of the INn_OSR registers.

Note that, if the 768kHz DMICCLKn frequency is selected for one or more of the digital microphone

input paths, then the Input Path sample rate (all input paths) is valid in the range 8kHz to 16kHz only.

Note that the DMICCLKn frequencies noted in Table 1 assume that the SYSCLK frequency is a

multiple of 6.144MHz (SYSCLK_FRAC=0). If the SYSCLK frequency is a multiple of 5.6448MHz

(SYSCLK_FRAC=1), then the DMICCLKn frequencies will be scaled accordingly.

CONDITION

DMICCLKn FREQUENCY

SIGNAL PASSBAND

INn_OSR = 00

1.536MHz

up to 20kHz

INn_OSR = 01

3.072MHz

up to 20kHz

INn_OSR = 11

768kHz

up to 8kHz

Table 1 DMICCLK Frequency

The voltage reference for each digital microphone interface is selectable, using the INn_DMIC_SUP

registers. Each interface may be referenced to MICVDD, or to the MICBIAS1, MICBIAS2 or

MICBIAS3 levels.

A stereo pair of digital microphones is connected as illustrated in Figure 17. In this configuration, the

microphones must be configured to ensure that the Left mic transmits a data bit when DMICCLK is

high, and the Right mic transmits a data bit when DMICCLK is low. The WM8998 samples the digital

microphone data at the end of each DMICCLK phase. Each microphone must tri-state its data output

when the other microphone is transmitting.

The DMICDAT2 pin supports mono input on the Left interface channel only. The DMIC2 microphone

ust be configured to ensure that it transmits a data bit when DMICCLK is high.

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