WM8998 datasheet(78/307 Pages) WOLFSON

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WM8998

Production Data

PD, October 2014, Rev 4.0

SPDIF OUTPUT GENERATOR

The WM8998 incorporates an IEC-60958-3 compatible S/PDIF output generator, as illustrated in

Figure 29; this provides a stereo S/PDIF output on a GPIO pin. The S/PDIF transmitter allows full

control over the S/PDIF validity bits and channel status information.

The input sources to the S/PDIF transmitter are selectable for each channel, and independent volume

control is provided for each path. The *TX1 and *TX2 registers control channels ‘A’ and ‘B’

(respectively) of the S/PDIF output.

The S/PDIF signal can be output directly on a GPIO pin. See “General Purpose Input / Output” to

configure a GPIO pin for this function.

Note that the S/PDIF signal cannot be selected as input to the digital mixers or signal processing

functions within the WM8998 digital core.

SPDIF1TX1MIX_VOL

SPDIF1TX2MIX_VOL

SPDIF1TX2MIX_SRC

SPDIF1TX1MIX_SRC

GPIO

(GPn = 07h)

S/PDIF

SPD1_ENA

SPD1_RATE

Channel ‘A’

Channel ‘B’

Figure 29 Digital Core S/PDIF Output Generator

The S/PDIF input control registers (see Figure 29) are located at register addresses R2048 (800h)

through to R2057 (809h).

The full list of digital mixer control registers is provided in the “Register Map” section (Register R1600

through to R2920). Generic register definitions are provided in Table 7.

The *_SRCn registers select the input source(s) for the two S/PDIF channels. Note that the selected

input source(s) must be synchronised to the SYSCLK clocking domain, and configured for the same

sample rate as the S/PDIF generator. Sample rate conversion functions are available to support

flexible interconnectivity - see “Asynchronous Sample Rate Converter (ASRC)” and “Isochronous

Sample Rate Converter (ISRC)”.

The sample rate of the S/PDIF generator is configured using the SPD1_RATE register - see Table 19.

The S/PDIF transmitter supports sample rates in the range 32kHz up to 192kHz. Note that sample

rate conversion is required when linking the S/PDIF generator to any signal chain that is

asynchronous and/or configured for a different sample rate.

The S/PDIF generator is enabled using the SPD1_ENA register bit, as described in Table 15.

The S/PDIF output contains audio data derived from the selected sources. Audio samples up to 24-bit

width can be accommodated. The Validity bits and the Channel Status bits in the S/PDIF data are

configured using the corresponding fields in registers R1474 (5C2h) to R1477 (5C5h).

Refer to S/PDIF specification (IEC 60958-3) for full details of the S/PDIF protocol and configuration

parameters.

WM8998 Datasheet(PDF) 78 Page - Wolfson Microelectronics plc

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