WM8998 datasheet(32/307 Pages) WOLFSON

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WM8998

Production Data

PD, October 2014, Rev 4.0

DIGITAL AUDIO INTERFACE - MASTER MODE

BCLK

(output)

LRCLK

(output)

TXDAT

(output)

RXDAT

(input)

tDD

tDH

tDSU

tLRD

tBCH

tBCL

tBCY

Figure 5 Audio Interface Timing - Master Mode

Note that BCLK and LRCLK outputs can be inverted if required; Figure 5 shows the default, non-

inverted polarity.

Test Conditions

The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted.

CLOAD = 15pF to 25pF (output pins). BCLK slew (10% to 90%) = 3.7ns to 5.6ns.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Interface Timing - Master Mode

AIFnBCLK cycle time

tBCY

AIFnLRCLK propagation delay from BCLK falling edge

tLRD

AIFnTXDAT propagation delay from BCLK falling edge

tDD

AIFnRXDAT setup time to BCLK rising edge

tDSU

AIFnRXDAT hold time from BCLK rising edge

tDH

Note:

The descriptions above assume non-inverted polarity of AIFnBCLK.

WM8998 Datasheet(PDF) 32 Page - Wolfson Microelectronics plc

WM8998 Datasheet(HTML) 32 Page - Wolfson Microelectronics plc

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