WM8998 datasheet(97/307 Pages) WOLFSON

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WM8998

PD, October 2014, Rev 4.0

ISOCHRONOUS SAMPLE RATE CONVERTER (ISRC)

The WM8998 supports multiple signal paths through the digital core. The Isochronous Sample Rate

Converters (ISRCs) provide sample rate conversion between synchronised sample rates on the

SYSCLK clock domain, or between synchronised sample rates on the ASYNCCLK clock domain.

There are two Isochronous Sample Rate Converters (ISRCs). ISRC1 provides four signal paths

between two different sample rates; ISRC2 provides two signal paths between two different sample

rates, as illustrated in Figure 36.

The sample rates associated with each ISRC can be set independently. Note that the two sample

rates associated with any single ISRC must both be referenced to the same clock domain (SYSCLK

or ASYNCCLK).

When an ISRC is used on the SYSCLK domain, then the associated sample rates may be selected

from SAMPLE_RATE_1, SAMPLE_RATE_2 or SAMPLE_RATE_3.

When an ISRC is used on the ASYNCCLK domain, then the associated sample rates are

ASYNC_SAMPLE_RATE_1 and ASYNC_SAMPLE_RATE_2.

See “Clocking and Sample Rates” for details of the sample rate control registers.

Each ISRC supports sample rates in the range 8kHz to 192kHz. The higher of the sample rates

associated with each ISRC must be an integer multiple of the lower sample rate; integer ratios in the

range 1 to 6 are supported on ISRC1; integer ratios in the range 1 to 24 are supported on ISRC2.

Each ISRC converts between a sample rate selected by ISRCn_FSL and a sample rate selected by

ISRCn_FSH, (where ‘n’ identifies the applicable ISRC 1 or 2). Note that, in each case, the higher of

the two sample rates must be selected by ISRCn_FSH.

The ISRCn ‘interpolation’ paths (increasing sample rate) are enabled using the ISRCn_INTm_ENA

The ISRCn ‘decimation’ paths (decreasing sample rate) are enabled using the ISRCn_DECm_ENA

A notch filter is provided in each of the ISRC paths; these are enabled using the

ISRCn_NOTCH_ENA bits. The filter is configured automatically according to the applicable sample

rate(s). It is recommended to enable the filter for typical applications. Disabling the filter will provide

maximum ‘pass’ bandwidth, at the expense of degraded stopband attenuation.

The WM8998 performs automatic checks to confirm that the SYSCLK frequency is high enough to

support the commanded ISRC and digital mixing functions. If an attempt is made to enable an ISRC

signal path, and there are insufficient SYSCLK cycles to support it, then the attempt will be

unsuccessful. (Note that any signal paths that are already active will not be affected under these

circumstances.)

The Underclocked Error condition can be monitored using the GPIO and/or Interrupt functions. See

“General Purpose Input / Output” and “Interrupts” for further details.

The status bits in Registers R1600 to R2920 indicate the status of each of the digital mixers. If an

Underclocked Error condition occurs, then these bits provide readback of which mixer(s) have been

successfully enabled.

The Isochronous Sample Rate Converter (ISRC) signal paths and control registers are illustrated in

Figure 36.

WM8998 Datasheet(PDF) 97 Page - Wolfson Microelectronics plc

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