WM8998 datasheet(33/307 Pages) WOLFSON

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Production Data

WM8998

PD, October 2014, Rev 4.0

DIGITAL AUDIO INTERFACE - SLAVE MODE

BCLK

(input)

LRCLK

(input)

TXDAT

(output)

RXDAT

(input)

tDSU

tDD

tDH

tLRH

tLRSU

tBCH

tBCL

tBCY

Figure 6 Audio Interface Timing - Slave Mode

Note that BCLK and LRCLK inputs can be inverted if required; Figure 6 shows the default, non-

inverted polarity.

Test Conditions

The following timing information is valid across the full range of recommended operating conditions.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Interface Timing - Slave Mode

AIFnBCLK cycle time

tBCY

AIFnBCLK pulse width high

tBCH

AIFnBCLK pulse width low

tBCL

AIFnLRCLK set-up time to BCLK rising edge

tLRSU

AIFnLRCLK hold time from BCLK rising edge

tLRH

AIFnRXDAT hold time from BCLK rising edge

tDH

AIFnTXDAT propagation delay from BCLK falling edge

tDD

AIFnRXDAT set-up time to BCLK rising edge

tDSU

Notes:

The descriptions above assume non-inverted polarity of AIFnBCLK.

When AIFnBCLK or AIFnLRCLK is selected as a source for SYSCLK or ASYNCCLK (either directly or via one of the FLLs), the

frequency must be within 1% of the applicable SYSCLK_FREQ or ASYNCCLK_FREQ register setting.

WM8998 Datasheet(PDF) 33 Page - Wolfson Microelectronics plc

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