WM8998 datasheet(45/307 Pages) WOLFSON

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Production Data

WM8998

PD, October 2014, Rev 4.0

INPUT SIGNAL PATH SAMPLE RATE CONTROL

The input signal paths may be selected as input to the digital mixers or signal processing functions

within the WM8998 digital core. The sample rate for the input signal paths is configured using the

IN_RATE register - see Table 19 within the “Digital Core” section.

Note that sample rate conversion is required when routing the input signal paths to any signal chain

that is asynchronous and/or configured for a different sample rate.

INPUT SIGNAL PATH CONFIGURATION

The WM8998 supports six input channels. Selectable combinations of analogue (mic or line) and

digital inputs are multiplexed into three input signal paths.

The input signal path configuration is selected using the INn_MODE and INnx_SRC registers (where

‘n’ identifies the associated input, and ‘x’ identifies the left/right channel, where applicable). The

external circuit configurations are illustrated on the previous pages.

A configurable high pass filter (HPF) is provided on the left and right channels of each input path. The

applicable cut-off frequency is selected using the IN_HPF_CUT register. The filter can be enabled on

each path independently using the IN1L_HPF, IN1R_HPF and IN2_HPF bits.

The analogue input signal paths (single-ended or differential) each incorporate a PGA to provide gain

in the range 0dB to +31dB in 1dB steps. Note that these PGAs do not provide pop suppression

functions; it is recommended that the gain should not be adjusted whilst the respective signal path is

enabled.

The analogue input PGA gain is controlled using the IN1L_PGA_VOL, IN1R_PGA_VOL and

IN2_PGA_VOL registers.

When the input signal path is configured for digital microphone input, the voltage reference for the

associated input/output pins is selectable using the INn_DMIC_SUP registers - each interface may be

referenced to MICVDD, or to the MICBIAS1, MICBIAS2 or MICBIAS3 levels.

When the input signal path is configured for digital microphone input, the respective DMICCLKn

frequency can be configured using the INn_OSR register bits.

A digital delay may be applied to any of the digital microphone input channels. This feature can be

used for phase adjustment of any digital input, including directional control of multiple microphones.

The delay is controlled using the IN1L_DMIC_DLY, IN1R_DMIC_DLY and IN2_DMIC_DLY registers.

The MICVDD voltage is generated by an internal Charge Pump and LDO Regulator. The MICBIAS1,

MICBIAS2 and MICBIAS3 outputs are derived from MICVDD - see “Charge Pumps, Regulators and

Voltage Reference”.

Under default register conditions, the input signal paths are configured for highest performance. This

can be adjusted using the INn_OSR registers, which provide control of the DMICCLKn frequency and

the ADC oversample rate.

The input signal paths are configured using the register bits described in Table 3.

WM8998 Datasheet(PDF) 45 Page - Wolfson Microelectronics plc