WM8998 datasheet(71/307 Pages) WOLFSON

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Production Data

WM8998

PD, October 2014, Rev 4.0

DRC Register Controls

The DRC control registers are described in Table 13.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R3585

(0E01h)

FX_Ctrl2

15:4

FX_STS [11:0]

000h

LHPF, DRC, EQ Enable Status

Indicates the status of each of the

respective signal processing

functions.

[11] = EQ4

[10] = EQ3

[9] = EQ2

[8] = EQ1

[7] = Reserved

[6] = Reserved

[5] = DRC1 (Right)

[4] = DRC1 (Left)

[3] = LHPF4

[2] = LHPF3

[1] = LHPF2

[0] = LHPF1

Each bit is coded as:

0 = Disabled

1 = Enabled

R3712

(0E80h)

DRC1 ctrl1

15:11

DRC1_SIG_DET

_RMS [4:0]

00h

DRC1 Signal Detect RMS

Threshold.

This is the RMS signal level for

signal detect to be indicated when

DRC1_SIG_DET_MODE=1.

00h = -30dB

01h = -31.5dB

…. (1.5dB steps)

1Eh = -75dB

1Fh = -76.5dB

10:9

DRC1_SIG_DET

_PK [1:0]

DRC1 Signal Detect Peak

Threshold.

This is the Peak/RMS ratio, or Crest

Factor, level for signal detect to be

indicated when

DRC1_SIG_DET_MODE=0.

00 = 12dB

01 = 18dB

10 = 24dB

11 = 30dB

DRC1_NG_ENA

DRC1 Noise Gate Enable

0 = Disabled

1 = Enabled

DRC1_SIG_DET

_MODE

DRC1 Signal Detect Mode

0 = Peak threshold mode

1 = RMS threshold mode

DRC1_SIG_DET

DRC1 Signal Detect Enable

0 = Disabled

1 = Enabled

DRC1_KNEE2_

OP_ENA

DRC1 KNEE2_OP Enable

0 = Disabled

1 = Enabled

DRC1_QR

DRC1 Quick-release Enable

0 = Disabled

1 = Enabled

WM8998 Datasheet(PDF) 71 Page - Wolfson Microelectronics plc

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