DP83953 datasheet(29/90 Pages) NSC

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4.0 Functional Description (Continued)

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Table 1. Pin Definitions for Options in the Mode Load Operation

Name

Program-

ming

Function

Effect when

Bit is 0

Effect when

Bit is 1

Function

SCRTY

Security

Mode

Non-Security

Mode

This bit configures RIC2A security feature options.

When D0 =0 LME, SME, ESA, EDA bits in the Port

Security Configuration Register (PSCR) are set globally.

When D0=1 security can still be done, but now the user

needs to set the above bits in the PSCR register.

TW2

5 bits

3 bits

This allows the user to select one of two values for the

repeater specification TW2 time. The lower limit (3 bits)

meets the IEEE specification. The upper limit (5 bits) is not

specification compliant but may provide users with higher

network throughput by avoiding spurious network activity

gaps when using coaxial (10BASE2, 10BASE5) network

segments.

CCLIM

The partition specification requires a port to be partitioned

after a certain number of consecutive collisions. The

RIC2A has two values available to allow users to customize

the partitioning algorithm to their environment. Please refer

to the Partition State Machine, in data sheet section 7.3.

LPPART

Selected

Not Selected

The RIC2A may be configured to partition a port if the

segment transceiver does not loopback data to the port

when the port is transmitting to it, as described in the

Partition State Machine.

OWCE

Selected

Not Selected

This configuration bit allows the on-chip partition algorithm

to include out of window collisions into the collisions it

monitors, as described in the Partition State Machine.

TXONLY

Selected

Not Selected

This configuration bit allows the on-chip partition algorithm

to restrict segment reconnection, as described in the

Partition State Machine.

DPART

Selected

Not Selected

The Partition state machines for all ports may be disabled

by writing a logic zero to this bit during the mode load

operation.

MIN/MAX

Minimum Mode Maximum Mode The operation of the display update block is controlled by

the value of this configuration bit, as described in the

Display Update Cycles section.

RA0

All ports (2 to 13) use the internal 10BASE-T transceivers.

(Internally configured)

RA1

RA2

BINV

Active High

Signals

Active Low Sig-

nals

This selection determines whether the Inter-RIC signals:

IRE, ACTN, ANYXN, COLN and Management bus signal

MCRS are active high or low.

RA3

EXPLL

External PLL

Internal PLL

If desired, the RIC2A may be used with an external

decoder, this configuration bit performs the selection.

RA4

resv

Not Permitted

Required

To ensure correct device operation, this bit must be written

with a logic one during the mode load operation.

DP83953 Datasheet(PDF) 29 Page - National Semiconductor (TI)

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