DP83953 datasheet(2/90 Pages) NSC

2 / 90 page

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General Description (continued)

The RIC2A repeater consists of two major functional

blocks: The segment specific block and the shared func-

tional blocks. The segment specific block incorporates rele-

vant IEEE specifications on a per port basis. The shared

functional blocks incorporate core logic for the entire IEEE

repeater unit. The core logic blocks consist of a repeater

receive multiplexor, a phase locked loop (PLL), a Manches-

ter decoder, an elasticity buffer, a transmit encoder and a

demultiplexor.

A larger repeater system may be constructed by cascading

several RIC2A devices via the Inter-RIC bus. This method

of cascading allows the RIC2A system to function as a sin-

gle repeater unit without introducing additional repeater

hops.

The RIC2A is configurable for specific applications. It pro-

vides port status information for LED array displays and a

simple interface for system processors. The RIC2A pos-

sesses multifunctional counters and status flag arrays to

facilitate network statistics gathering, as well as a serial

Hub Management Interface Bus for collecting, event data in

managed hub applications.

Table of Contents

1.0

Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.0

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.0

Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.0

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1

Summary of DP83953 RIC2A Feature

Enhancements from DP83952 RIC II . . . . . . . . . 12

4.2

Overview Of RIC2A Functions . . . . . . . . . . . . . . . 12

4.3

Description Of Repeater Operations . . . . . . . . . . 14

4.4

Examples Of Packet Repetition

Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.5

Description Of Hardware Connection For Inter-ric

Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.6

Processor and Display Interface . . . . . . . . . . . . . 28

4.7

Description Of Hardware Connection For Processor

And Display Interface . . . . . . . . . . . . . . . . . . . . . . 30

5.0

HUB Management Support . . . . . . . . . . . . . . . . . . . . . 35

5.1

Event Counting Function . . . . . . . . . . . . . . . . . . 35

5.2

Event Record Function . . . . . . . . . . . . . . . . . . . . 36

5.3

Management Interface Operation . . . . . . . . . . . . 37

5.4

Description of Hardware Connection for

Management Interface . . . . . . . . . . . . . . . . . . . . 43

6.0

Port Block Functions . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.1

Transceiver Functions . . . . . . . . . . . . . . . . . . . . 44

6.2

Segment Partition . . . . . . . . . . . . . . . . . . . . . . . . 47

6.3

Port Status Register Functions . . . . . . . . . . . . . . 47

6.4

Local Ports and Expected Activity . . . . . . . . . . . 49

7.0

RIC2A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.0

Board Layout Recommendations . . . . . . . . . . . . . . . 75

9.0

DC and AC Specification . . . . . . . . . . . . . . . . . . . . . . 77

10.0

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 90

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