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DP83953 Datasheet(PDF) 66 Page - National Semiconductor (TI) |
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DP83953 Datasheet(HTML) 66 Page - National Semiconductor (TI) |
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66 / 90 page ![]() 66 www.national.com 7.0 RIC2A Registers (Continued) Lower Event Information Register (Lower EIR) (Page 1H Address 1FH) Port Event Count Register (Pages 2H and 3H) The Event Count Register (ECR) shows the instantaneous value of the specified port's 16 bit counter. The counter incre- ments when an enabled event occurs. The counter may be cleared when it is read, and prevented from rolling over when the maximum count is reached, by setting the appropriate control bits in the Upper Event Count mask register. Since the RIC2A's processor port is octal and the counters are 16 bits long, a temporary holding register is employed for register reads. When one of the counters is read, either high or low byte first, all 16 bits of the counter are transferred to a holding register. Provided the next read cycle to the counter array accesses the same counter's other byte, then the read cycle accesses the holding register. This avoids the problem of events occurring in between the two processor reads and indi- cating a false count value. In order to enter a new value to the holding register a different counter must be accessed, or the same counter byte must be re-read. D7 D6 D5 D4 D3 D2 D1 D0 DLU resv resv ER13 ER12 ER11 ER10 ER9 Bit R/W Symbol Description D0 R ER9 0: Flag found not generated by event on port 9 1: Flag found generated by event on port 9 D1 R ER10 0: Flag found not generated by event on port 10 1: Flag found generated by event on port 10 D2 R ER11 0: Flag found not generated by event on port 11 1: Flag found generated by event on port 11 D3 R ER12 0: Flag found not generated by event on port 12 1: Flag found generated by event on port 12 D4 R ER13 0: Flag found not generated by event on port 13 1: Flag found generated by event on port 13 D5 R resv Reserved for Future Use reads as a logic 0 D6 R resv Reserved for Future Use reads as a logic 0 D7 R/W DLU Disable the LED Updates: This bit disables the LED display updates for a faster processor register access 0: Re-enable the LED update cycle.(Note) 1: Disable the LED update cycles Note: The LED update cycle will be re-enabled only when the network and the RIC2A internal state ma- chines are idle Lower Byte D7 D6 D5 D4 D3 D2 D1 D0 EC7 EC6 EC5 EC4 EC3 EC2 EC1 EC0 Upper Byte D7 D6 D5 D4 D3 D2 D1 D0 EC15 EC14 EC13 EC12 EC11 EC10 EC9 EC8 |
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