DP83953 datasheet(13/90 Pages) NSC

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4.0 Functional Description (Continued)

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the case of a source address mismatch, the RIC2A will

immediately switch to a random bit pattern on both the

local transmitting ports and the IRB.

The main state machine operates in conjunction with a

series of counter timers. These timers will ensure that all

associated IEEE specification times (referred to as the

TW1 to TW6 times) are met.

An IEEE repeater system must meet the same signal jitter

performance as any other receiving node attached to a net-

work

segment.

Consequently,

phase

locked

loop

Manchester decoder is required so that the packet may be

decoded, and the jitter accumulated over the receiving seg-

ment recovered. The decode logic outputs data in non

return to zero (NRZ) format with an associated clock and

enable. This format allows the packet to be conveniently

transferred to other attached devices, such as network con-

trollers and other repeaters through the Inter-RIC bus

(IRB). The data may then be re-encoded into Manchester

data and transmitted.

During reception and/or transmission through the physical

layer transceivers a loss of bits in the preamble field of a

packet may occur. This loss must be replaced according to

the IEEE repeater specification. To accomplish this, an

elasticity buffer is employed to restore a full length pream-

ble upon transmission.

The Sequence of Operation

Soon after the network segment receiving a packet has

been identified, the RIC2A will transmit the preamble pat-

tern (1010...) to all other network segments. While the pre-

amble is being transmitted, the elasticity buffer will monitor

the decoded received clock and data signals via the Inter-

RIC bus (IRB). When the start of frame delimiter (SFD) is

detected, the received data stream will be written into the

elasticity buffer. The removal of stored data from the elas-

ticity buffer for re-transmission is not allowed until a valid

length preamble pattern has been transmitted.

Internal CAMs

To implement the security features, the RIC2A uses two

sets of Content Addressable Memory (CAMs) for address

comparison: port CAMs, and shared CAMs.

Port CAMs

The RIC2A provides two CAM locations (48 bits wide) per

port for comparison. The two CAM locations contain source

address(es) for incoming packets on their respective ports.

The addresses can be stored (CPU access) or learned

(Learn Mode). While in learning mode, LME=1, external

processor access is not advised or allowed, since the con-

tents of the two CAM registers may not be valid. Once the

addresses are learned, they are used to make compari-

sons between the source and destination addresses. An

address can only be learned when a packet has been

received with a valid CRC. External processor/logic access

to these registers is fine while learning is not in progress,

LME=0 in the port security configuration register.

Shared CAMs

The RIC2A provides thirty-two shareable CAM locations

(48 bits wide) to store Ethernet addresses associated with

the ports. The Ethernet addresses are stored by writing to

these CAM locations where the addresses could be shared

among the thirteen ports. By using shared CAMs, multiple

Ethernet addresses can be associated with a single port,

or multiple ports can be allocated to a single Ethernet

address. After the destination address of the received

packet is completely buffered, the RIC2A will compare this

address with the stored addresses in the CAM locations.

The source address is compared in a similar fashion.

These shared CAM locations are user defined only, and will

not be filled in learning mode.

A CAM entry could be shared among the thirteen local

ports. This is done through a 16-bit CAM Location Mask

CLMR, therefore there are 32 registers for the 32 CAM

entries.

Since register access is performed on a byte basis, six

write cycles must be completed to program the Ethernet

address into the CAM. The upper three bits of the CAM

Location Mask Register (CLMR) act as a pointer indicating

which byte of the 6-byte address will be accessed next.

This pointer will increment every time a read or write cycle

is completed to the CAM entry. The pointer starts at 1, indi-

cating the least significant byte of the address.

Four additional registers are provided to validate the 32

shared CAM entries and are referred to as the Shared

CAM Validation Registers 1-4 (SCVR 1-4, Page 9H,

Address 16-19H). Each bit of the SCVR is mapped to one

CAM location. An address in the CAM location will only be

valid when a corresponding bit Address Valid (ADV bit) has

been set in this register. The RIC2A will include only valid

CAM locations for address comparison.

The contents of all CAM locations are unknown at power

up. This is not a problem since corresponding Address

Valid (ADV) bits are not set for each CAM. Therefore, com-

parisons will not take place with the CAM contents.

Inter-RIC Bus (IRB) Interface

A RIC2A based repeater system may be constructed to

support many more network attachments than those avail-

able through a single chip. The split functions described

earlier, allow data packets and collision status to be trans-

ferred between multiple RIC2As while allowing the system

to function as a single logical repeater. Since all RIC2As in

a multiple RIC2A system are identical and capable of per-

forming all repetition functions, the failure of one RIC2A will

not cause a failure of the entire system. This is an impor-

tant issue, especially with respect to large multi-port

repeaters.

In a multi-RIC2A system, the RIC2As can communicate

through a specialized interface known as the Inter-RIC

bus(IRB). This bus allows the data packet to be transferred

from the receiving RIC2A to other RIC2As in the system.

Each RIC2A then transmits the datastream to its seg-

ments.

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