DP83953 datasheet(12/90 Pages) NSC

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4.0 Functional Description

The IEEE 802.3 repeater specification delineates the func-

tional criteria that all compliant repeater systems must

adhere to. An implementation of these requirements

strongly suggest a multiport modular design style. In such

a design, functionality is split between those tasks common

to all data channels and those exclusive to each individual

channel. The RIC2A follows this approach. Certain func-

tional blocks are replicated for each network attachment,

(also known as a repeater port), and others are shared.

The following subsections provide an overview of the

RIC2A architecture. First, RIC2A feature enhancements

from the RIC II is discussed. Then, the RIC2A functional

blocks are described.

4.1 Summary of DP83953 RIC2A Feature En-

hancements from DP83952 RIC II

1. The DP83953 RIC2A integrates transmit filters and driv-

ers on a per port basis. These additional features allow

a system developer to add little more than external isola-

tion transformers in order to build fully secured/managed

hub products.

2. The functionality of the DP83953 is essentially similar to

DP83952, but some of the pin definitions have been

modified to reflect the new integrated drivers and trans-

mit filters. Therefore, the RIC2A is

not a drop in replace-

ment for the RICII. Additionally, power and ground pin

locations have been rearranged to accommodate addi-

tional pins.

3. Integrated network port drivers provide controlled rise

and fall time output signals. These port drivers will facili-

tate EMI compliance without procuring additional com-

ponents.

4. Compared to DP83952, the DP83953 requires additional

current drive. The additional current is required to imple-

ment the new integrated drivers and transmit filters.

4.2 Overview Of RIC2A Functions

Segment Specific Block: Network Port

As shown in the block diagram, the segment specific blocks

consist of

A logic section and a physical layer interface section.

The logic block is required for performing repeater oper-

ations upon that particular segment. It is known as the

“port” logic since it is the access “port” the segment has

to the rest of the network.

This function is repeated 13 times in the RIC2A (one for

each port) and is shown on the right side of the block dia-

gram, Figure 1.

The physical layer interface depends upon the port. Port 1

has an AUI compliant interface for use with AUI compatible

transceiver boxes and cable. Ports 2 to 13 are twisted pair

ports.

The four distinct functions inside the port logic block are:

1. The Port State Machine "PSM" performs data and colli-

sion repetition as described by the IEEE repeater speci-

fication. For example, it may determine if this port should

be receiving from or transmitting to a particular network

segment.

2. The Port Partition Logic implements the segment parti-

tioning algorithm. This algorithm is defined by the IEEE

specification and is used to protect the network from mal-

functioning segments.

3. The Port Status Register reflects the current status of the

port. The system processor may access this register to

obtain port status information or to configure certain port

options, such as port disable.

4. The Port security configuration logic determines if the

transmitted or received packet will contain intact or pseu-

do random data. This logic consists of two dedicated

CAM locations per port for learning, storing, and compar-

ing port source addresses.

Shared Functional Blocks: Repeater Core Logic

The shared functional blocks consists of the repeater Main

State Machine (MSM), Timers, a 32 bit Elasticity Buffer,

PLL Decoder, Receive and Transmit Multiplexors, and

Security Logic with 32 shareable CAM locations. These

blocks perform the majority of the operations needed to ful-

fill the requirements of the IEEE repeater specification.

When a packet is received by a port it is then sent via the

Receive Multiplexor to the PLL Decoder. Notification of the

data and collision status is sent to the MSM through the

receive multiplexor and collision activity status signals. This

enables the MSM to determine the source and type of data

to be transmitted and eventually repeated to all ports. This

information may be valid data or the jam pattern.

According to the IEEE repeater specifications, after a colli-

sion has been determined, the transmit data will be

replaced with a jam pattern consisting of a alternating ones

and zeros. (e.g. 1010...) for at least 96 bit times. If a colli-

sion occurs during the preamble, the address field, the type

field, or the data field the RIC2A will immediately switch to

the jam pattern to be transmitted to all ports.

If the RIC2A is configured for the "non-secure" mode, the

valid received data is transmitted to all of the other ports,

except the port which is receiving the packet.

If the RIC2A is configured for the "secure" mode, the

source and destination addresses within each packet are

first checked against the addresses of the local and shared

CAMs assigned to the port. Based on this comparison, and

the port configuration will be either:

1. A pseudo random bit pattern may be generated in the

data field of the designated “secure” packet and then

transmitted to their respective port(s). Or,

2. The received data may be transmitted intact.

The data always remains intact on the Inter-RIC bus (IRB

to be described later) to allow any cascaded repeaters to

compare all destination addresses with their local CAMs. In

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