DP83953 datasheet(20/90 Pages) NSC

20 / 90 page

4.0 Functional Description (Continued)

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Figure 5 shows two RIC2As A and B, daisy chained

together with RIC2A-A positioned at the top of the chain. If

a packet is received at port B1 of RIC2A-B, and then

repeated to the other ports in the system (non-secure

mode). Figure 6 shows the functional timing diagram for

the packet repetition signals. In this example only two ports

in the system are shown. In non-secure mode, the other

ports also repeat the packet. It also indicates the operation

of the RIC2As' state machines in so far as can be seen by

observing the Inter-RIC bus. For reference, the repeater's

state transitions are shown in terms of the states defined

by the IEEE specification. The location of

PORT N is also

shown. The following section describes the repeater and

Inter-RIC bus transitions shown in Figure 6.

The repeater activity is stimulated by the data signal

received by port B1. The RIC2As in the system are alerted

to forthcoming repeater operation by the falling edges on

the ACKI and ACKO daisy chain and the ACTN bus signal.

Following a defined start up delay the repeater moves to

the

SEND PREAMBLE state. The RIC2A system utilizes

the start up delay to perform port arbitration. When packet

transmission

begins,

the

RIC2A

system

enters

the

REPEAT state. The expected, for normal packet repetition,

sequence of repeater states,

SEND PREAMBLE, SEND

SFD and SEND DATA are followed, but are not visible at

the Inter-RIC bus. They are then merged into a single

REPEAT state. Similarly, the

WAIT and IDLE states appear

as a combined Inter-RIC bus IDLE state.

Once a REPEAT operation has begun (e.g. the repeater

leaves the

IDLE state), it is required to transmit at least 96

bits of data or jam/preamble onto its network segments. If

the duration of the received signal from

PORT N is shorter

than 96 bits, the repeater transitions to the

RECEIVE COL-

LISION state (described later). This behavior is known as

fragment extension.

After the packet data has been repeated, including the

emptying of the RIC2As' elasticity buffers, the RIC2A per-

forms the

Tw1 transmit recovery operation. This is per-

formed during the

WAIT state shown in the repeater state

diagram.

Figure 5. RIC2A System Topology

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