DP83953 datasheet(37/90 Pages) NSC

37 / 90 page

5.0 HUB MANAGEMENT SUPPORT (Continued)

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Short Event reception (SE): This flag goes active if the

received packet is less than 74 bits long and no collision

occurs during reception.

5.3 Management Interface Operation

The Hub Management interface provides a mechanism to

combine repeater status information with packet informa-

tion to form a hub management packet. A serial bus inter-

face consisting of carrier sense, receive clock and receive

data is designed to connect one or more RIC2A's over a

backplane bus to another device, such as the DP83932

“SONICTM” controller. The SONIC combined with the

RIC2As form a powerful entity for network statistics gather-

ing.

The management interface consists of four pins:

The first three signals will emulate the interface between an

Ethernet controller and a phase locked loop decoder (such

as the DP83932 SONIC and the DP83910 SNI). These sig-

nals are driven by the RIC2A that receives the packet. The

MRXC and MRXD are comprised of a NRZ serial data

stream compatible with the DP83932. The PCOMP signal

is driven by logic circuitry on the processor board. The

actual data stream transferred as MRXD is derived from

the transferred data (IRD) on the Inter-RIC bus. The differ-

ence between these two data streams are:

1. At the end of packet repetition a hub management status

field is appended to the data stream. This status field,

consisting of 7 bytes, is shown in Table 6, and Figure 14.

The information is obtained from several packet status

registers, which are described below. In accordance with

the IEEE Specification the least significant bit of a byte is

transmitted first.

2. While the data of the repeated packet is being trans-

ferred over the management bus, the received clock sig-

nals on the MRXC pin may be inhibited. This is controlled

by the Packet Compress pin PCOMP. If PCOMP is as-

serted during repetition of the packet then MRXC signals

are inhibited when the number of bytes (after SFD) trans-

ferred over the management bus equals the number dis-

played in the Packet Compress Decode Register. This

PCOMP signal, which may be generated early in the

packet's repetition. The packet compression feature re-

duces the amount of memory required to buffer packets

as they are received and are waiting to be processed by

hub management software. In this application, an ad-

dress decoder, which forms part of the packet compress

logic, would monitor the address fields as they are re-

ceived over the management bus. If the destination ad-

dress is not the address of the management node inside

the hub, then packet compression could be employed. In

this manner only the portion of the packet meaningful for

hub management interrogation (i.e., the address fields,)

is transferred to the SONIC and buffered into memory.

If the repeated packet ends before PCOMP is asserted

or before the required number of bytes have been trans-

ferred, then the hub management status field is directly

appended to the received data at a byte boundary. If the

repeated packet is significantly longer than the value in

the Decode Register requires, and PCOMP is asserted,

the status fields will be delayed until the end of packet

repetition. During this delay period MRXC clocks are in-

hibited, but the MCRS signal remains asserted.

Note: If

PCOMP is asserted late in the packet, i.e., after the number of

bytes defined by the packet compression register, then packet compression

will not occur.

The Management Interface may be fine tuned to meet the

timing considerations of the SONIC and the access time of

its associated packet memory. This refinement may be per-

formed in two ways:

1. The default mode of operation of the Management inter-

face is to only transfer packets over the bus which have

a start of frame delimiter. Thus "packets" that are only

preamble/jam and do not convey any source or destina-

tion address information are inhibited. This filtering may

be disabled by writing a logic zero to the Management In-

terface Configuration or "MIFCON" bit in the Manage-

ment

and

Interrupt

Configuration

See

Section 7.0 for details.

2. The Management bus has been designed to accommo-

date situations of maximum network utilization, for exam-

ple, when collision generated fragments occur. (These

collision fragments may violate the IEEE 802.3 IFG

specification.) The IFG required by the SONIC is a func-

tion of the time taken to release space in the receive

FIFO and to perform end of packet processing (write sta-

tus information into memory). These functions are prima-

rily memory operations and consequently depend upon

bus latency and the memory access time of the system.

In order to allow the system designer some discretion in

choosing the speed of this memory, the RIC2A may be

configured to protect the SONIC from a potential FIFO

overflow condition. This is performed by utilizing the In-

terFrame Gap (IFG) Threshold Select Register.

The value (plus one) held in this register defines the min-

imum allowable InterFrame Gap on the management

bus, measured in network bit times. If the gap is smaller

than this number, MCRS is asserted but MXRC clocks

are inhibited. Consequently, no data is transferred. So,

the system designer may decide whether or not to gather

statistics or to monitor a subset on all packets, even

though they only occur with very small IFGs.

The status field, shown in Table 6, contains information of

six different types. They are contained in seven Packet Sta-

tus Registers "PSRs":

1. The RIC2A and port address fields [PSR(0) and (1)] can

uniquely identify the repeater port receiving the packet

out of a potential maximum of 832 ports sharing the

same management bus (64 RIC2As each with 13 ports).

MRXC

Management Receive Clock - 10MHz NRZ

Clock output.

MCRS

Management Carrier Sense - Input/ Output

indicating of valid data stream.

MRXD

Management Receive Data - NRZ Data output

synchronous to MRXC

PCOMP

Packet Compress - Input to truncate the

packet's data field.

DP83953 Datasheet(PDF) 37 Page - National Semiconductor (TI)

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