DP83953 datasheet(59/90 Pages) NSC

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7.0 RIC2A Registers (Continued)

Real Time Interrupt Register (Address 0FH)

The Real Time Interrupt register (RTI) contains information which may change on a packet by packet basis. Any remain-

ing interrupts which have not been serviced before the following packet is transmitted are cleared. Since multiple interrupt

sources may be displayed by the RTI a priority scheme is implemented. A read cycle to the RTI gives the interrupt source

and an address vector indicating the RIC2A port that generated the interrupt.

The order of priority for the display of interrupt information is as follows (in secure mode only):

1. Source Address Mismatch (feature of the RIC2A that is not present in the RIC.)

2. The receive source of network activity (Port N),

3. The first RIC2A port showing collision,

4. A port partitioned or reconnected.

During the repetition of a single packet it is possible that multiple ports may be partitioned or alternatively reconnected.

The ports have equal priority in displaying partition/reconnection information. This data is derived from the ports by the

RTI register as it polls consecutively around the ports.

Reading the RTI clears the particular interrupt for all cases. If no interrupt sources are active, the RTI returns a no valid

interrupt status.

The following table shows the mapping of interrupt sources onto the D3 to D0 pins. Essentially each of the three interrupt

sources has a dedicated bit in this field. If a read to the RTI produces a low logic level on one of these bits then the inter-

rupt source may be directly decoded. Associated with the source of the interrupt is the port where the event is occurring.

If no unmasked events (receive, collision, etc.) have occurred when the RTI is read, then an all ones pattern is driven by

the RIC2A onto the data pins.

IVCTR3

IVCTR2

IVCTR1

IVCTR0

ISRC3

ISRC2

ISRC1

ISRC0

Bit

R/W

Symbol

Access

Description

D(3:0)

ISCR(3:0)

Interrupt Source

These four bits indicate the reason why the interrupt was generated.

D(7:4)

IVCTR(3:0)

Interrupt Vector

This field defines the port address responsible for generating the interrupt.

Comments

PA3

PA2

PA1

PA0

Source Address Mismatch

PA(3:0) = port address for the mismatch

PA3

PA2

PA1

PA0

first collision

PA(3:0) = collision port address

PA3

PA2

PA1

PA0

receive

PA(3:0) = receive port address

PA3

PA2

PA1

PA0

partition reconnection

PA(3:0) = partition port address

no valid interrupt

DP83953 Datasheet(PDF) 59 Page - National Semiconductor (TI)

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