DP83953 datasheet(36/90 Pages) NSC

36 / 90 page

5.0 HUB MANAGEMENT SUPPORT (Continued)

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The port event counters may also be controlled by the

Counter Decrement (CDEC) pin. As the name suggests, a

logic low state on this pin will decrement all the counters by

a single value. The pulses on CDEC are internally synchro-

nized and scheduled to avoid any conflict with the "up

counting" activity. If an “up count” and a “down count” occur

simultaneously, then the “down count” is delayed until the

“up count” has completed. This combination of up and

down counting capability enables the RIC2A's on-chip

counters to provide a simple rolling average, or be used as

extensions of larger external counters.

Note: If the FWF option is enabled then the count down operation is disabled

from those registers which have reached FFFF Hex and consequently have

been frozen. Thus, the FWF and

CDEC bits will be set to provide rate indi-

cation. A frozen counter indicates that a rate has gone out of bounds, due to

incrementing too fast or too slowly. If the low count and high count decodes

are employed as either interrupts or poll cycles, the direction of the rate ex-

cursion may be determined.

New Hub Management Counters

The are 13 more 8 bit counters on the RIC2A than provided

on the DP83950 RIC. These counters will count events

specified in the Event Count and Interrupt Mask Register 2

(ECIMR2), such as Frame Check Sequence, Frame Align-

ment Error, Partition, Out of Window Collision. Also, this

control bits.

It should be noted that Counter Decrement (CDEC) will not

be used with the ECMR2. Also, no real time or event log-

ging interrupt will be generated for this register.

Reading the Event Counters

The RIC2A's external data bus is eight bits wide. Since the

event counters are 16 bits long, two processor read cycles

are required to read the counter value. In order to ensure

correct counter values and simultaneously allow event

counts and processor accesses, values are stored in a

temporary holding register.

A read cycle to either the

lower or upper byte of a counter causes both bytes to be

latched into the temporary holding register. Thus, when the

other byte of the counter is obtained, the temporary holding

ensures that the upper and lower bytes contain the value

sampled at the same instant in time.

There are no restrictions concerning whether the upper or

lower byte is read first. However, to ensure the "same

instance value" is obtained, the reads of the upper then

lower byte (or vice versa) should be performed as consecu-

tive reads of the counter array. Other “non counter” regis-

ters may be read in between these read cycles and write

cycles may be performed. If another counter is read, or the

same byte of the original counter is read again, then the

holding register is updated from the counter array, and the

unread byte is lost.

If the reset on read option is employed, then the counter is

reset after the transfer to the holding register is performed.

Processor read and write cycles are scheduled to avoid

conflict with count up or count down operations. In the case

of a processor read, the count value is stable as it is loaded

into the holding register. In the case of a processor write,

the newly written value is stable enough to be incremented

or decremented by any subsequent count operation. Dur-

ing the period of time when the MLOAD pin is low, (power

on reset) all counters are reset to zero and all count masks

are forced into the disabled state. Section 7.0 of the data

sheet details the address location of the port event

counters.

5.2 Event Record Function

As stated previously, each repeater port has its own 8 bit

Event Recording status register. Each bit may be dedicated

to log the occurrence of a particular event (see Section 7.0

for detailed description). The Event Recording Mask Regis-

ter controls the logging of these events. Additionally, the

particular mask bit must be set to record an event. Similar

to the scheme employed for the event counters, the

recorded events are latched during the repetition of a

packet then automatically loaded into the recording regis-

ters at the end of packet transmission. When one of the

unmasked events occurs, that particular port register bit is

set. The register bits for all of the ports are logically "ORed"

together to produce a Flag Found "FF" signal. The Page

Select Register contains the Flag Found indicator. Addi-

tionally, if the appropriate mask bit is enabled in the Man-

agement and Interrupt Configuration Register then an

interrupt may be generated

A processor read cycle to an Event Record Register resets

any bits set in that register. Read operations are scheduled

to guarantee that data does not change during the cycle.

Any internal bit setting event that immediately follows a pro-

cessor read will be successful. Events that may be

recorded are described below:

Jabber Protection (JAB): This flag goes active if the

length of a received packet causes the repeater state

machine to enter into the Jabber Protect state.

Elasticity Buffer Error (ELBER): This goes active if a

buffer underflow or overflow condition occurs during packet

reception. The flag is held inactive if a collision occurs dur-

ing packet reception or if a phase lock error has already

occurred during packet reception.

Phase Lock Error (PLER): A phase lock error is caused if

the phase lock loop decoder loses lock during packet

reception. A phase lock onto the received data stream may

not be recoverable later in the packet and data errors may

have occurred. This flag is held inactive if a collision

occurs.

Non SFD Packet (NSFD): If a packet is received and the

start of frame delimiter (SFD) is not detected, this flag will

go active. The flag is held inactive if a collision occurs dur-

ing packet reception.

Out of Window Collision (OWC): The out of window colli-

sion flag goes active when a port experiences a collision

outside of the network slot time.

Partition (PART): This flag goes active when a port

becomes partitioned.

Bad Link (BDLNK): This flag goes active when a 10Base-

T port has entered the link lost state.

DP83953 Datasheet(PDF) 36 Page - National Semiconductor (TI)

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