DP83953 datasheet(67/90 Pages) NSC

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7.0 RIC2A Registers (Continued)

Port Event Count Register 2 (PECR-2) (Page 4H Addresses 11H to 1DH)

The Port Event Count Register 2 (PECR-2) shows the instantaneous value of the specified port's 8 - bit counter. The

counter increments when an enabled event occurs. The counter may be cleared when it is read, and prevented from roll-

ing over when the maximum count is reached, by setting the appropriate control bits in the ECIMR - 2 register.

Port Security Configuration Register (PSCR) (Pages 4H, 5H, 6H, 8H, 9H)

This register sets up the various security modes for the RIC2A. It provides port specific information such as enabling/dis-

abling the security mode, passing broadcast packets, etc. In addition, comparison on destination address, source address,

or both can be selected. The system can also qualify learning mode on a per port basis.

Note: Bit D0 is only for the port CAMs, and not for the shared CAMs

EC7

EC6

EC5

EC4

EC3

EC2

EC1

EC0

res

EDA

ESA

SAM

MCE

BCE

SME

LME

Bit

R/W

Symbol

Description

R/W

LME

Learning Mode

0: Disable Learn Mode for port CAMs.

1: Enable Learn Mode for port CAMs.

R/W

SME

Security Mode

0: Disable Security Mode.

1: Enable Security Mode.

R/W

BCE

Accept Broadcast: Enables the repeater to pass/repeat a packet with an all 1's

destination address.

0: Replace the broadcast packets with random packets.

1: Pass broadcast packets.

Note: SA mismatch is still valid for broadcast packets.

R/W

MCE

Accept Multicast: Enables the repeater to pass/repeat a packet with the LSB of

'1' in the most significant byte of the destination address.

0: Replace the multicast packets with random packets.

1: Pass multicast packets.

Note: SA mismatch is still valid for multicast packets.

SAM

Source Address Match/Mismatch

0: Source address match occurred for the packet.

1: Source address mismatch occurred for the packet.

R/W

ESA

Source Address Security

0: Do not employ source address to implement security.

1: Employ source address to implement security.

R/W

EDA

Destination Address Security

0: Do not employ destination address to implement security.

1: Employ destination address to implement security.

resv

Reserved for Future Use

reads as a logic 0

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