DP83953 datasheet(14/90 Pages) NSC

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4.0 Functional Description (Continued)

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The notification of collisions occurring across the network

is just as important as data transfers. The Inter-RIC bus

has a set of status lines capable of conveying collision

information between RIC2As in order to ensure that their

main state machines operate in the appropriate manner.

LED Interface and Hub Management Function

Repeater systems usually possess optical displays indicat-

ing network activity and the status of specific repeater

operations. The display update block of the RIC2A can pro-

vide the system designer with a wide variety of indicators.

The updates are completely autonomous and merely

require SSI logic to drive the display devices, usually made

up of light emitting diodes (LEDs). The status display is

very flexible and allows the user to choose appropriate indi-

cators for the specification of his equipment.

The RIC2A was designed for those interested in imple-

menting large repeaters with hub management capabilities.

Hub management uses the unique position of repeaters in

a network to gather statistics about the network segments

they are attached to. Important events are gathered by the

management block from logic blocks throughout the chip.

These events are then stored in on-chip latches, or counted

in on-chip counters according to the developer’s supplied

latching and counting masks.

The fundamental task of a hub management system imple-

mentation is to associate the current packet and any man-

agement status information with the network segment. An

example could be keeping track of packets received on a

repeater’s ports. An ideal system would place the com-

bined data packet and status field in system memory for

future examination by hub management software. The

main function of the RIC2A's hub management support

logic is to provide this function.

To accomplish this task, the RIC2A utilizes a dedicated hub

management interface. This is similar to the Inter-RIC bus

since it allows the data packet to be recovered from the

receiving RIC2A. Unlike the Inter-RIC bus, the intended

recipient is not another RIC2A, but typical National Semi-

conductor's DP83932 ("SONIC™"). This dedicated bus

allows a management status field to be appended at the

end of each packet without affecting the operation of the

entire repeater system.

In addition to the counters provided on the RIC DP83950B,

the RIC2A implements thirteen more (8 bit wide) counters.

These counters will count events specified in the Event

Count and Interrupt Mask Register2 (ECIMR2). These

include items such as Frame Check Sequences, Frame

Alignment Errors, Partitions, and Out of Window Collisions.

This register also includes "Reset On Read" and "Freeze

When Full" control bits.

It should be noted that Counter Decrement (CDEC) will not

be used with the ECMR2. Also, real time or event logging

interrupts (RTI or ELI) will not be generated for this register.

Processor Interface

The RIC2A's processor interface uses an octal bi-direc-

tional data bus in order to interface to a system processor.

The RIC2A has on-chip registers to indicate the status of

the hub management functions, chip configuration, and

port status. These registers are accessed by placing the

respective address at the Register Address (RA4 - RA0)

input pins.

Display update cycles and processor accesses occur utiliz-

ing the same data bus. An on-chip arbiter in the proces-

sor/display block schedules and controls the accesses and

ensures the correct information is written into the display

latches. During the display update cycles the RIC2A

behaves as a master of its data bus. This is the default

state of the data bus. Consequently, a TRI-STATE buffer

must be placed between the RIC2A and the system pro-

cessor's data bus. This ensures that bus contention prob-

lems are avoided during simultaneous display update

cycles and processor accesses of other devices on the

system bus. When the processor accesses a RIC2A regis-

ter, the RIC2A enables the data buffer and selects the

operation, either input or output, of the data pins.

For faster register accesses, the RIC2A provides the added

feature of disabling display update cycles. Setting the Dis-

able LED Update bit, DLU in the Lower Event Information

update cycles. This disables the shared mode of the data

bus, leaving the RIC2A in slave access mode. In this mode,

the maximum read/write cycle time is reduced to approxi-

mately 400 ns.

4.3 Description Of Repeater Operations

In order to implement a multi-chip repeater system that

behaves as a single logical repeater, special considerations

must be taken into account with respect to the data path

used for packet repetition. For example, we must consider

where in the data path specific operations such as

Manchester decoding and elasticity buffering are per-

formed. Additionally, the system state machines, which uti-

lize available network activity signals, must accommodate

various packet repetition and collision scenarios according

to the IEEE repeater specification.

The RIC2A contains two types of interacting state

machines. They are:

1. Port State Machines (PSMs) Every network attachment

has its own PSM.

2. Main State Machine (MSM) This state machine controls

the shared functional blocks as shown in the block dia-

gram Figure 1.

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