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DP83953 Datasheet(PDF) 39 Page - National Semiconductor (TI) |
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DP83953 Datasheet(HTML) 39 Page - National Semiconductor (TI) |
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39 / 90 page ![]() 5.0 HUB MANAGEMENT SUPPORT (Continued) 39 www.national.com Table 6. Hub Management Status Field Packet status Register PSR D7 D6 D5 D4 D3 D2 D1 D0 PSR(0) A5 A4 A3 A2 A1 A0 PCOMPD resv PSR(1) CRCER FAE COL CLN PA3 PA2 PA1 PA0 PSR(2) SE OWC NSFD PLER ELBER JAB CBT9 CBT8 PSR(3) Collision Bit Timer CBT7 CBT6 CBT5 CBT4 CBT3 CBT2 CBT1 CBT0 PSR(4) Lower Repeat Byte Count RBY7 RBY6 RBY5 RBY4 RBY3 RBY2 RBY1 RBY0 PSR(5) Upper Repeat Byte Count Note 2 MPS=0 ---------- MPS=1 RBY15 ------------ resv RBY14 ----------- resv RBY13 ----------- resv RBY12 ----------- SAM RBY11 ----------- RUNT RBY10 ----------- RBY10 RBY9 ---------- RBY9 RBY8 ----------- RBY8 PSR(6) Inter Frame Gap Bit Timer IBT7 IBT6 IBT5 IBT4 IBT3 IBT2 IBT1 IBT0 Note 1: These registers may only be reliably accessed via the management interface. Due to the nature of these registers they may not be accessed (read or write cycles) via the processor interface. Note 2: When MPS (Modify Packet Status) bit in the Global Security Register is: MPS=0, Do not modify Packet Status Register 5. The RIC2A PSR5 is the same as the RIC PSR5. MPS=1, The PSR5 register is modified in the RIC2A. Figure 14. Management Bus Packet Status Register TIming |
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