DP83953 datasheet(62/90 Pages) NSC

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7.0 RIC2A Registers (Continued)

Event Count and Interrupt Mask Register 2 (ECIMR-2) (Page 0H Address 15H)

The bits in this register effect the Port Event Count Register 2, PECR-2 on Page 4, Addresses 11H to 1DH.

res

ISAM

FWF-2

ROR-2

OWCC-2

PARTC-2

FAEC

FCSC

Bit

R/W

Symbol

Description

R/W

FCSC

Frame Check Sequence Count Enable: This bit enables counting the packets

with frame check sequence error.

0: Disable the frame check sequence count.

1: Enable the frame check sequence count.

R/W

FAEC

Frame Alignment Error Count Enable: This bit enables counting the packets

with frame alignment error.

0: Disable the frame alignment error count.

1: Enable the frame alignment error count.

R/W

PARTC-2

Partition Count Enable: This bit enables recording of partition events.

0: Disable the partition count.

1: Enable the partition count.

R/W

OWCC-2

Out of Window Collision Count Enable: This bit enables counting of out of

window collision events.

0: Disable the out of window collision count.

1: Enable the out of window collision count.

R/W

ROR-2

Reset On Read: This bit enables the counter register to reset upon reading the

port event's counter.

0: No effect upon reading the register contents.

1: The counter register is reset by reading the contents of the

R/W

FWF-2

Freeze When Full: This bit controls the freezing of the Event Count registers

when the counter is full (FF Hex).

0: No effect on the event count register.

1: Freeze the event count register when the counter is full.

R/W

ISAM

Interrupt on the Source Address Mismatch Mask

0: Interrupts will be generated on a source address mismatch

mask. (RTI pin becomes active.)

1: No interrupts are generated.

resv

Reserved for Future Use

reads as a logic 0

DP83953 Datasheet(PDF) 62 Page - National Semiconductor (TI)

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