DP83953 datasheet(63/90 Pages) NSC

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7.0 RIC2A Registers (Continued)

Interrupt and Management Configuration Register (Page 0H Address 16H)

This register powers up with all bits set to one and must be initialized by a processor write cycle before any events will

generate interrupts.

RIC2A Address Register (Page 0H Address 17H)

This register may be used to differentiate between RIC2As in a multi-RIC2A repeater system. The contents of this register

form part of the information available through the management bus.

IFC

IHC

ILC

IFF

IREC

ICOL

IPART

MIFCON

bit

R/W

Symbol

Description

R/W

MIFCON

Management Interface Configuration

0: All Packets repeated are transmitted over the Management bus.

1: Packets repeated by the RIC2A that do not have Start of Frame Delimiters are

not transmitted over the Management bus.

R/W

IPART

Interrupt on Partition

0: Interrupts will be generated (RTI pin goes active) if a port becomes Partitioned.

1: No interrupts are generated by this condition.

R/W

ICOL

Interrupt on Collision

0: Interrupts will be generated (RTI pin goes active) if this RIC2A has a port that

experiences a collision (single RIC2A applications,) or contains a port that

experiences a receive collision or is the first port to suffer a transmit collision in a

packet in Multi-RIC2A applications.

1: No interrupts are generated by this condition.

R/W

IREC

Interrupt on Receive

0: Interrupts will be generated (RTI pin goes active) if this RIC2A contains the

receive port for packet or collision activity.

1: No interrupts are generated by this condition.

R/W

IFF

Interrupt on Flag Found

0: Interrupts will be generated (ELI pin goes active) if one or more than one of the

flags in the flag array is true.

1: No interrupts are generated by this condition.

R/W

ILC

Interrupt on Low Count

0: Interrupt generated (ELI pin goes active) when one or more of the Event

Counters holds a value less than 256 counts.

1: no effect

R/W

IHC

Interrupt on High Count

0: Interrupt generated (ELI pin goes active) when one or more of the Event

Counters holds a value in excess of 49152 counts.

1: No effect

R/W

IFC

Interrupt on Full Counter

0: Interrupt generated (ELI pin goes active) when one or more of the Event

Counters is full.

1: No effect

resv

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