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DP83953 Datasheet(PDF) 60 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # DP83953
Description  Repeater Interface Controller with Security Features, Internal Drivers and Integrated Filters
PDF  90 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83953 Datasheet(HTML) 60 Page - National Semiconductor (TI)

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7.0 RIC2A Registers (Continued)
Page Select Register ((All pages) Address 10H)
The Page Select register performs two functions:
1. It enables switches to be made between register pages,
2. It provides status information regarding the Event Logging Interrupts.
Device Type Register (Page 0H Address 11H)
This register may be used to distinguish different revisions of RIC. It will return the value 91 H for the DP83953 RIC2A
device. It will return the value 8XH for the DP83952 RICII device, or the value 0XH for the DP83950 RIC device. Write
operations to this register have no effect upon the contents.
Lower Event Count Mask Register (Page 0H Address 12H)
Note: 1 = enable, 0 = disable
D7
D6
D5
D4
D3
D2
D1
D0
FC
HC
LC
FF
PSEL3
PSEL2
PSEL1
PSEL0
bit
R/W
Symbol
Description
D(3:0)
R/W
PSEL(3:0)
Page Select Bits: When read these bits indicate the currently selected Upper
Register Array Page. Write cycles to these locations facilitates page swapping. The
page select bits are latched on the rising edge of the read strobe.
D4
R
FF
Flag Found: This indicates one of the unmasked event recording latches has been
set.
D5
R
LC
Low Count: This indicates one of the port event counters has a value less than
00FF Hex.
D6
R
HC
High Count: This indicates one of the port event counters has a value greater than
C000 Hex.
D7
R
FC
Full Counter: This indicates one of the port event counters has a value equal to
FFFF Hex.
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
1
0
0
X
X
D7
D6
D5
D4
D3
D2
D1
D0
BDLNKC
PARTC
RECC
SEC
NSFDC
PLERC
ELBERC
JABC
Bit
R/W
Symbol
Description
D0
R/W
JABC
Jabber Count Enable: Enables recording of Jabber Protect events.
D1
R/W
ELBERC
Elasticity Buffer Error Count Enable: Enables recording of Elasticity Buffer Error
events.
D2
R/W
PLERC
Phase Lock Error Count Enable: Enables recording of Carrier Error events.
D3
R/W
NSFDC
Non SFD Count Enable: Enables recording of Non SFD packet events.
D4
R/W
SEC
Short Event Count Enable: Enables recording of Short events.
D5
R/W
RECC
Receive Count Enable: Enables recording of Packet Receive (port N status)
events that do not suffer collisions.
D6
R/W
PARTC
Partition Count Enable: Enables recording of Partition events.
D7
R/W
BDLNKC
Bad Link Count Enable: Enables recording of Bad Link events.



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