DP83953 datasheet(56/90 Pages) NSC

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7.0 RIC2A Registers (Continued)

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RIC2A Status and Configuration Register (Address 00H)

The lower portion of this register contains real time information concerning the operation of the RIC2A. The D7 bit repre-

sent the chosen configuration of the transceiver interface employed.

BINV

resv

APART

JAB

AREC

ACOL

resv

Bit

R/W

Symbol

Access

Description

resv

Reserved for future use

Reads as a logic 1.

ACOL

Any Collisions

0: A collision is occurring at one or more of the RIC2A's ports.

1: No collisions.

AREC

Any Receive

0: one of the RIC2A's ports is the current packet or collision receiver.

1: No packet or collision reception within this RIC2A.

JAB

Jabber Protect

0: The RIC2A has been forced into jabber protect state by one of its ports or by

another port on the Inter-RIC bus, (Multi-RIC2A operations).

1: No jabber protect conditions exist.

APART

Any Partition

0: One or more ports are partitioned.

1: No ports are partitioned.

resv

Reserved

resv

Reserved

Reads as a logic 1.

BINV

Bus Invert

This register bit informs whether the Inter-RIC signals: IRE, ACTN, ANYXN, COLN

and Management bus signal MCRS are:

0: active high.

1: active low.

DP83953 Datasheet(PDF) 56 Page - National Semiconductor (TI)

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