DP83953 datasheet(7/90 Pages) NSC

7 / 90 page

2.0 Pin Descriptions (Continued)

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TT = TTL compatible, B = Bi-directional, C = CMOS compatible, OD = Open Drain, I = Input, O = Output,

Z = high impedance

RTI

REAL TIME INTERRUPT: A low level on the RTI output indi-

cates the RIC2A's real time (packet specific) interrupt logic re-

quires CPU attention. The interrupt is cleared by reading the

Real Time Interrupt Status register. All interrupt sources may be

masked.

CDEC

COUNTER DECREMENT: A rising edge on the CDEC input

strobe decrements all of the RIC2A's Port Event Counters by

one. This input is internally synchronized and if necessary the

operation of the signal is delayed if there is a simultaneous in-

ternally generated counting operation.

WRITE STROBE: Strobe from the CPU used to write an internal

READ STROBE: Strobe from the CPU used to read an internal

MLOAD

DEVICE RESET AND MODE LOAD: When this input cycles

back up from low to high, all of the RIC2A's state machines,

counters and network ports are reset and held inactive. On the

rising edge of MLOAD the logic levels present on the D0 - 7 pins

and RA0 - RA4 inputs are latched into the RIC2A's configuration

registers. The rising edge of MLOAD also signals the beginning

of the display test operation. The clock signal must be present

on the CLKIN pin during MLOAD assertion and de-assertion.

DP83953 Datasheet(PDF) 7 Page - National Semiconductor (TI)