DP83953 datasheet(35/90 Pages) NSC

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5.0 HUB MANAGEMENT SUPPORT

The RIC2A provides information regarding the status of its

ports and the packets being repeated. This data is avail-

able in three forms:

1. Counted Events - Network events accumulated into the

RIC2A's 16 bit Event Counter Registers.

2. Recorded Events - Network events that set bits in the

Event Record Registers.

3. Hub Management Status Packets- This is the informa-

tion sent over the Management Bus in a serial format to

be decoded by an Ethernet Controller board.

The processor interface provides access to all counted and

recorded event information. This data is port specific and

may be used to generate interrupts via the Event Logging

Interrupt “ELI” pin. Since the information is specific to each

port, each repeater port has its own event record register

and event counter. The counters and event record registers

have user definable masks which enable them to be config-

ured to count and record a variety of events. The counters

and record registers are designed to be used together so

that detailed information (i.e., a count value) can be held

on-chip for a specific network condition. More general infor-

mation, i.e. the occurrence of certain types of events, may

be retained in on-chip latches. Thus, the user can configure

the counters to increment upon a rapidly occurring event

(most likely to be used to count collisions), and the record

registers may log the occurrence of less frequent error con-

ditions such as jabber protect packets.

5.1 Event Counting Function

The counters may increment upon the occurrence of one of

the categories of event as described below.

Potential sources for Counter increment:

Jabber Protection (JAB): The port counter increments if

the length of a received packet from its associated port

causes the repeater state machine to enter the jabber pro-

tect state.

Elasticity Buffer Error (ELBER): The port counter incre-

ments if an Elasticity Buffer underflow or overflow condition

occurs during packet reception. This flag is held inactive if

a collision occurs during packet reception or if a phase lock

error, described below, has already occurred during packet

reception.

Phase Lock Error (PLER): A phase lock error is caused if

the phase lock loop decoder loses lock during packet

reception. Phase lock onto the received data stream may

or may not be recovered later in the packet, so data errors

may have occurred. This flag is held inactive if a collision

occurs.

Non SFD Packet (NSFD): If a packet is received and the

start of frame delimiter (SFD) is not detected the port

counter will increment. NSFD counting is inhibited if the

packet experiences a collision.

Out of Window Collision (OWC): The OWC flag for a port

goes active when a port experiences a collision outside of

the network slot time.

Transmit Collision (TXCOL): The TXCOL flag is enabled

when the repeater experiences a transmit collision.

Receive Collision (RXCOL): The RXCOL flag for a port

goes active when the port is the receive source of network

activity and suffers a collision, provided no other network

segments experience collisions. At that point, the receive

collision flag for the receiving port will be set.

Partition (PART): The port counter increments when a

port becomes partitioned.

Bad Link (BDLNK): The port counter increments when a

10BASE-T port has entered the link lost state.

Short Event reception (SE): The port counter increments

if the received packet is less than 74 bits long and no colli-

sion occurs during reception.

Packet Reception (REC): When a packet is received the

port counter increments.

In order to utilize the counters the user must choose, from

the above list, the desired statistics for counting. This

counter mask information must be written to the appropri-

ate registers (i.e. Upper and Lower Event Count Mask Reg-

isters). For the exact bit patterns of these registers please

read Section 7.0 of the data sheet.

If the counters are configured to count network collisions

and the appropriate masks have been set, then whenever a

collision occurs on a segment, this information will be

latched by the hub management support logic. At the end

of repetition of the packet the collision status, respective to

each port, is loaded into that port's counter. This operation

is completely autonomous and requires no processor inter-

vention.

Each counter is 16 bits long and may be directly read by

the processor. Additionally each counter has a number of

decodes to indicate the current value of the count. There

are three decodes:

low count (a value of 00FF Hex and under),

high count (a value of C000 Hex and above),

full count (a value of FFFF Hex).

The decodes from each counter are logically "ORed"

together and may be used as interrupts for the ELI interrupt

pin. Additionally, the status of these bits may be observed

by reading the Page Select Register. In order to enable

these threshold interrupts, the appropriate interrupt mask

bit must be written to the Management and Interrupt Con-

figuration Register. See Section 7.0 for register details.

In addition to their event masking functions, the Upper

Event Counting Mask Register (UECMR) possesses two

bits that control operation of the counters. The Reset On

Read “ROR” bit resets the counters after performing a pro-

cessor read cycle. If this ROR bit is not set, which is used

to zero the counters, then the counters must be either writ-

ten with zeros by the processor or allowed to rollover to all

zeros. The Freeze When Full “FWF” bit prevents counter

rollover by inhibiting count up cycles (these cycles happen

when chosen events occur), thereby freezing that particular

counter at FFFF Hex.

DP83953 Datasheet(PDF) 35 Page - National Semiconductor (TI)

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