TMS320C6711 datasheet(119/129 Pages) TI

119 / 129 page

TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088L − FEBRUARY 1999 − REVISED MAY 2004

119

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 55)

[C6711]

C6711-100

C6711-150

UNIT

NO.

MASTER

SLAVE

UNIT

MIN

MAX

MIN

MAX

tsu(DRV-CKXH)

Setup time, DR valid before CLKX high

2 − 6P

th(CKXH-DRV)

Hold time, DR valid after CLKX high

6 + 12P

timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 55)

[C6711B]

NO.

C6711B-100

C6711B-150

C6711BGFNA-100

UNIT

NO.

MASTER

SLAVE

UNIT

MIN

MAX

MIN

MAX

tsu(DRV-CKXH)

Setup time, DR valid before CLKX high

2 − 6P

th(CKXH-DRV)

Hold time, DR valid after CLKX high

14 + 12P

timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 55)

[C6711C/C6711D]

NO.

GDPA-167

−200

−250 (6711D)

UNIT

NO.

MASTER

SLAVE

UNIT

MIN

MAX

MIN

MAX

tsu(DRV-CKXH)

Setup time, DR valid before CLKX high

2 − 6P

th(CKXH-DRV)

Hold time, DR valid after CLKX high

5 + 12P

† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

TMS320C6711 Datasheet(PDF) 119 Page - Texas Instruments

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