TMS320C6711 datasheet(123/129 Pages) TI

123 / 129 page

TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D

FLOATING-POINT DIGITAL SIGNAL PROCESSORS

SPRS088L − FEBRUARY 1999 − REVISED MAY 2004

123

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GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORT TIMING [C6711C/C6711D ONLY]

timing requirements for GPIO inputs†‡ (see Figure 57)

NO.

GDPA-167

−200

−250 (6711D)

UNIT

MIN

MAX

tw(GPIH)

Pulse duration, GPIx high

tw(GPIL)

Pulse duration, GPIx low

† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

‡ The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the DSP recognize the GPIx

changes through software polling of the GPIO register, the GPIx duration must be extended to at least 24P to allow the DSP enough time to access

the GPIO register through the CFGBUS.

switching characteristics over recommended operating conditions for GPIO outputs†§

(see Figure 57)

NO.

PARAMETER

GDPA-167

−200

−250 (6711D)

UNIT

MIN

MAX

tw(GPOH)

Pulse duration, GPOx high

12P − 3

tw(GPOL)

Pulse duration, GPOx low

12P − 3

† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

§ The number of CFGBUS cycles between two back-to-back CFGBUS writes to the GPIO register is 12 SYSCLK1 cycles; therefore, the minimum

GPOx pulse width is 12P.

GPIx

GPOx

Figure 57. GPIO Port Timing

TMS320C6711 Datasheet(PDF) 123 Page - Texas Instruments

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