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TMS320C6711 Datasheet(PDF) 120 Page - Texas Instruments |
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TMS320C6711 Datasheet(HTML) 120 Page - Texas Instruments |
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120 / 129 page  TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D FLOATING-POINT DIGITAL SIGNAL PROCESSORS SPRS088L − FEBRUARY 1999 − REVISED MAY 2004 120 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 55) [C6711] NO PARAMETER C6711-100 C6711-150 UNIT NO. PARAMETER MASTER§ SLAVE UNIT MIN MAX MIN MAX 1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶ H − 9 H + 9 ns 2 td(FXL-CKXL) Delay time, FSX low to CLKX low# T − 9 T + 9 ns 3 td(CKXH-DXV) Delay time, CLKX high to DX valid −9 9 6P + 4 10P + 20 ns 6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high −9 9 6P + 3 10P + 20 ns 7 td(FXL-DXV) Delay time, FSX low to DX valid L − 9 L + 9 4P + 2 8P + 20 ns switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 55) [C6711B] NO. PARAMETER C6711B-100 C6711B-150 C6711BGFNA-100 UNIT NO. PARAMETER MASTER§ SLAVE UNIT MIN MAX MIN MAX 1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶ H − 10 H + 10 ns 2 td(FXL-CKXL) Delay time, FSX low to CLKX low# T − 10 T + 10 ns 3 td(CKXH-DXV) Delay time, CLKX high to DX valid −10 10 6P + 4 10P + 25 ns 6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high −10 10 6P + 3 10P + 25 ns 7 td(FXL-DXV) Delay time, FSX low to DX valid L − 10 L + 10 4P + 2 8P + 25 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). |
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