PM8313 datasheet(29/192 Pages) PMC

29 / 192 page

PM8313 D3MX

DATA SHEET

PMC-920702

ISSUE 5

M13 MULTIPLEXER

Pin Name

Type

Pin No. Function

RDLCLK/

RDLINT

Output

The receive data link clock (RDLCLK) signal is

active when an external HDLC receiver is

selected (the REXHDLC bit in the Master

HDLC Configuration Register is a logic 1). The

RDLCLK signal provides timing for the external

processing of the path maintenance data link

signal extracted by the DS3 FRMR. RDLCLK is

updated on the falling edge of the ROHCLK

signal and cycles 3 times per M-frame.

RDLCLK is nominally a 28.2 kHz clock, which

is low for at least 1.9 µs per cycle.

The data link interrupt (RDLINT) signals is

active when the internal HDLC receiver is

selected (the REXHDLC in the Master HDLC

Configuration Register bit is a logic 0). The

RDLINT signal is asserted when an event

occurs which changes the status of the HDLC

receiver. RDLINT is updated on the falling

edge of the ROHCLK signal. RDLINT is

deasserted when the Interrupt Enable/Status

default RDLINT is an active low open-drain

output, but can be configured as active high.

Typically, RDLINT would be connected to an

external DMA device. If the supervising

microprocessor is desired to service the RFDL,

this output can be wired-ORed with the INTB

output when RDLINT is configured as an

active-low open drain output.

PM8313 Datasheet(PDF) 29 Page - PMC-Sierra, Inc