PM8313 datasheet(48/192 Pages) PMC

48 / 192 page

PM8313 D3MX

DATA SHEET

PMC-920702

ISSUE 5

M13 MULTIPLEXER

8.5

DS3 Transmitter

The TRAN T3 transmitter integrates circuitry required to insert the overhead bits

into a DS3 bit stream and produce a B3ZS encoded signal. The TRAN is directly

compatible with the M23 and C-bit parity DS3 formats specified in ANSI T1.107a.

When configured for the C-bit parity application, all overhead bits are inserted.

When configured for the M23 application, all overhead bits except the stuff

control bits (the C-bits) are inserted; the C-bits must be inserted by upstream

circuitry (such as the MX23 TSB). The TRAN provides indication of the M-frame

boundary in the outgoing DS3 signal. The DS3 signal may optionally be encoded

in B3ZS format.

Status signals such as far end receive failure, the alarm indication signal, and the

idle signal can be inserted when their transmission is enabled by internal register

bits.

A valid pair of P-bits is automatically calculated and inserted by the TRAN. When

C-bit parity mode is selected, the C-bit parity bits, and far end block error (FEBE)

indications are automatically inserted.

When enabled for C-bit parity operation, the alarm and control channel and the

path maintenance data link are input serially at 9.4 kbit/s and 28.2 kbit/s,

respectively, and inserted into the appropriate overhead bits. Codes to be

inserted into the alarm and control channel are sourced by the XBOC bit-

oriented code transmitter TSB. LAPD messages to be inserted in the path

maintenance data link are sourced by the XFDL data link transmitter.

The TRAN supports diagnostic modes in which it inserts P or C-bit parity errors,

F-bit framing errors, M-bit framing errors, invalid X or P-bits, line code violations,

or all-zeros.

8.6

Path Maintenance Data Link Transmitter

The XFDL Data Link Transmitter is designed to provide a serial path

maintenance HDLC data link for the DS3 C-bit parity application. The XFDL is

used under microprocessor to transmit HDLC data frames. It performs all of the

data serialization, CRC generation, zero-bit stuffing, as well as flag, idle, and

abort sequence insertion. Data to be transmitted is provided on an interrupt-

driven basis by writing to a double-buffered transmit data register. Upon

completion of the frames, a CRC-CCITT frame check sequence is transmitted,

followed by idle flag sequences. If the transmit data register underflows, an abort

sequence is automatically transmitted.

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