PM8313 datasheet(30/192 Pages) PMC

30 / 192 page

PM8313 D3MX

DATA SHEET

PMC-920702

ISSUE 5

M13 MULTIPLEXER

Pin Name

Type

Pin No. Function

RDLSIG/

RDLEOM

Output

The receive data link (RDLSIG) signal is active

when an external HDLC receiver is selected

(the REXHDLC bit in the corresponding Master

HDLC Configuration Register is a logic 1). The

RDLSIG signal carries bits extracted from the

three C-bits in M-subframe #5 by the DS3

framer. RDLSIG is held high when C-bit parity

mode is not enabled. RDLSIG is updated on

the falling edge of the corresponding RDLCLK

signal.

The receive end of message (RDLEOM) signal

is active if the internal HDLC receiver is

selected (the REXHDLC bit in the Master

HDLC Configuration Register is a logic 0). The

RDLEOM signal is asserted when the last byte

of a sequence is read from the HDLC receiver,

or if the receiver's buffer overruns. RDLEOM is

updated on the falling edge of the ROHCLK

signal. RDLEOM is deasserted when the

Interrupt Enable/Status Register is read in the

HDLC Receiver. By default, RDLEOM is an

active low open-drain output, but can be

configured as active high.

Typically, RDLEOM would be connected to the

supervising microprocessor when an external

DMA is used, signaling the microprocessor that

a complete message is ready. In this case the

RDLEOM is configured as an active-low open

drain output and wired-ORed with the INTB

output.

PM8313 Datasheet(PDF) 30 Page - PMC-Sierra, Inc