LAN9250 datasheet(230/421 Pages) MICROCHIP

230 / 421 page

LAN9250

DS00001913A-page 230

 2015 Microchip Technology Inc.

If Loss of Signal mode is not selected, then Signal Detect mode is selected by the FXSDENA strap input pin. When

greater than 1 V (typ.), Signal Detect mode is enabled, when less than 1 V (typ.), copper twisted pair is enabled.

Table 12-8 summarizes the selection.

12.2.17

REQUIRED ETHERNET MAGNETICS (100BASE-TX AND 10BASE-T)

The magnetics selected for use with the device should be an Auto-MDIX style magnetic, which is widely available from

several vendors. Please review the SMSC/Microchip Application note 8.13 “Suggested Magnetics” for the latest quali-

fied and suggested magnetics. A list of vendors and part numbers are provided within the application note.

12.2.18

PHY REGISTERS

The PHY registers are indirectly accessed through the Host MAC MII Access Register (HMAC_MII_ACC) and Host

MAC MII Data Register (HMAC_MII_DATA).

A list of the MII serial accessible Control and Status registers and their corresponding register index numbers is included

in Table 12-9. Each individual PHY is assigned a unique PHY address as detailed in Section 12.1.1, "PHY Addressing,"

on page 210.

In addition to the MII serial accessible Control and Status registers, a set of indirectly accessible registers provides sup-

port for the IEEE 802.3 Section 45.2 MDIO Manageable Device (MMD) Registers. A list of these registers and their cor-

responding register index numbers is included in Table 12-15.

Note:

The Digital Reset (DIGITAL_RST) bit will cause the EEPROM Loader to reload the configuration strap val-

ues into the PHY registers and to reset all other PHY registers to their default values. An EEPROM RELOAD

command via the EEPROM Command Register (E2P_CMD) also has the same effect.

Control and Status Registers

Table 12-9 provides a list of supported registers. Register details, including bit definitions, are provided in the following

subsections.

Unless otherwise specified, reserved fields must be written with zeros if the register is written.

Note:

The FXSDENA strap input pin is shared with the FXSDA pin. As such, the LVPECL levels ensure that the

input is greater than 1 V (typ.) and that Signal Detect mode is selected. When TP copper is desired, the

Signal Detect input function is not required and the pin should be set to 0 V.

Care must be taken such that an non-powered or disabled transceiver does not load the Signal Detect input

below the valid LVPECL level.

TABLE 12-8:

100BASE-FX LOS, SD AND TP COPPER SELECTION

FXLOSEN

FXSDENA

PHY Mode

<1 V (typ.)

TP copper

>1 V (typ.)

100BASE-FX Signal Detect

>1 V (typ.)

n/a

100BASE-FX LOS

TABLE 12-9:

PHY MII SERIALLY ACCESSIBLE CONTROL AND STATUS REGISTERS

Index

Group

PHY Basic Control Register (PHY_BASIC_CONTROL)

Basic

PHY Basic Status Register (PHY_BASIC_STATUS)

Basic

PHY Identification MSB Register (PHY_ID_MSB)

Extended

PHY Identification LSB Register (PHY_ID_LSB)

Extended

PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV)

Extended

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