LAN9250 datasheet(1/421 Pages) MICROCHIP

Part #	LAN9250

Description	Integrated Ethernet PHY with HP Auto-MDIX

PDF	421 Pages

Scroll/Zoom	100%

Manufacturer	MICROCHIP [Microchip Technology]

Direct Link	http://www.microchip.com

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1 / 421 page

 2015 Microchip Technology Inc.

DS00001913A-page 1

Highlights

• 16-bit 10/100 industrial Ethernet controller & PHY

• Interfaces to most 8/16-bit embedded controllers

and 32-bit embedded controllers with an 8/16-bit

bus

• Integrated Ethernet PHY with HP Auto-MDIX

• Integrated Ethernet MAC

• Compliant with Energy Efficient Ethernet 802.3az

• Wake on LAN (WoL) support

• Integrated IEEE 1588v2 hardware time stamp unit

• Cable diagnostic support

• 1.8V to 3.3V variable voltage I/O

• Integrated 1.2V regulator for single 3.3V operation

• Low pin count and small body size package

Target Applications

• Cable, satellite, and IP set-top boxes

• Digital televisions & video recorders

• VoIP/Video phone systems

• Home gateways

• Test/Measurement equipment

• Industrial automation systems

Key Benefits

• Single-chip Ethernet controller

- Fully compliant with IEEE 802.3/802.3u standards

- Integrated Ethernet MAC and PHY

- 10BASE-T and 100BASE-TX support

- 100BASE-FX support for external fiber transceiver

- Automatic polarity detection and correction

(HP Auto-MDIX)

- Full- and Half-duplex support

- Full-duplex flow control

- Backpressure for half-duplex flow control

- Preamble generation and removal

- Automatic 32-bit CRC generation and checking

- Automatic payload padding and pad removal

- Loop-back modes

• Eliminates dropped packets

- Internal buffer memory can store over 200 packets

- Automatic PAUSE and back-pressure flow control

• Flexible address filtering modes

- One 48-bit perfect address

- 64 hash-filtered multicast addresses

- Pass all multicast

- Promiscuous mode

- Inverse filtering

- Pass all incoming with status report

- Disable reception of broadcast packets

• 8/16-Bit Host Bus Interface

- Indexed register or multiplexed bus

- 16Kbyte FIFO with flexible TX/RX allocation

- SPI / Quad SPI support

• IEEE 1588v2 hardware time stamp unit

- Global 64-bit tunable clock

- Ordinary clock: master / slave, one-step / two-step, end-

to-end / peer-to-peer delay

- Fully programmable timestamp on TX or RX,

timestamp on GPIO

- 64-bit timer comparator event generation (GPIO or IRQ)

• Comprehensive power management features

- 3 power-down levels

- Wake on link status change (energy detect)

- Magic packet wakeup, Wake on LAN (WoL), wake on

broadcast, wake on perfect DA

- Wakeup indicator event signal

- Link status change

• Power and I/O

- Integrated power-on reset circuit

- Latch-up performance exceeds 150mA

per EIA/JESD78, Class II

- JEDEC Class 3A ESD performance

- Single 3.3V power supply

(integrated 1.2V regulator)

• Additional Features

- Multifunction GPIOs

- General purpose timer

- Optional EEPROM interface

- Ability to use low cost 25MHz crystal for reduced BOM

• Packaging

- Pb-free RoHS compliant 64-pin QFN or 64-pin TQFP-

EP

• Available in commercial, industrial, and extended

industrial* temp. ranges

*Extended temp. (105ºC) is supported only in the 64-QFN with an

external voltage regulator (internal regulator must be disabled) and

2.5V (typ) Ethernet magnetics.

LAN9250

10/100 Industrial Ethernet Controller & PHY

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