LAN9250 datasheet(47/421 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001913A-page 47

LAN9250

The Host MAC WoL detection can be left functioning by using the HMAC_SYS_ONLY_DIS bit instead, which keeps the

RX and TX clocks enabled. As a safety precaution, in order for this bit to be set, it must be written as a 1 two consecutive

times. A write of a 0 will reset the count.

6.3.3.2

Disabling The 1588 Unit

The entire 1588 Unit, including the CSRs, may be disabled by setting the 1588_DIS bit in the Power Management Con-

trol Register (PMT_CTRL). As a safety precaution, in order for this bit to be set, it must be written as a 1 two consecutive

times. A write of a 0 will reset the count.

The Timestamp Unit, including CSRs, may be disabled by setting the appropriate 1588_TSU_DIS bit in the Power Man-

agement Control Register (PMT_CTRL). As a safety precaution, in order for a bit to be set, it must be written as a 1 two

consecutive times. A write of a 0 will reset the count.

6.3.3.3

PHY Power Down

The PHY may be placed into power-down as described in Section 12.2.10, "PHY Power-Down Modes," on page 222.

6.3.3.4

LED Pins Power Down

All LED outputs may be disabled by setting the LED_DIS bit in the Power Management Control Register (PMT_CTRL).

Open-drain / open-source LEDs are un-driven. Push-pull LEDs are still driven but are set to their inactive state.

APPLICATION NOTE:

Individual LEDs can be disabled by setting them open-drain GPIO outputs with a data value

of 1.

6.3.4

CHIP LEVEL POWER MANAGEMENT

The device supports power-down modes to allow applications to minimize power consumption.

Power is reduced by disabling the clocks as outlined in Table 6-2, "Power Management States". All configuration data

is saved when in any power state. Register contents are not affected unless specifically indicated in the register descrip-

tion.

There is one normal operating power state, D0, and three power saving states: D1, D2 and D3. Although appropriate

for various wake-up detection functions, the power states do not directly enable and are not enforced by these functions.

: Normal Mode - This is the normal mode of operation of this device. In this mode, all functionality is available.

This mode is entered automatically on any chip-level reset (POR, RST# pin reset).

: System Clocks Disabled, XTAL, PLL and network clocks enabled - In this low power mode, all clocks derived

from the PLL clock are disabled. The network clocks remain enabled if supplied by the PHY. The crystal oscillator

and the PLL remain enabled. Exit from this mode may be done manually or automatically.

This mode is useful for MAC WoL mode, where the PHY is enabled and the MAC is configured for WoL detection.

This mode could be used for PHY General Power Down mode and PHY Energy Detect Power Down mode.

: System Clocks Disabled, PLL disable requested, XTAL enabled - In this low power mode, all clocks derived

from the PLL clock are disabled. The PLL is allowed to be disabled (and will disable if the PHY is in either Energy

Detect or General Power Down). The network clocks remain enabled if supplied by the PHY. The crystal oscillator

remains enabled. Exit from this mode may be done manually or automatically.

This mode is useful for PHY Energy Detect Power Down mode. This mode could be used for PHY General Power

Down mode.

: System Clocks Disabled, PLL disabled, XTAL disabled - In this low power mode, all clocks derived from the

PLL clock are disabled. The PLL will be disabled. The crystal oscillator is disabled. Exit from this mode may be

only be done manually.

This mode is useful for PHY General Power Down mode.

The Host must place the PHY into General Power Down mode by setting the Power Down (PHY_PWR_DWN)

bit of the PHY Basic Control Register (PHY_BASIC_CONTROL) before setting this power state.

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